Hong-Sun Hwang

Three-Dimensional Integration Approach to High-Density Memory Devices

U-In Chung, Hojung Kim, Sanghun Jeon, 2011, IEEE Transactions on Electron Devices.

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2011, IEICE Trans. Electron..

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2010, 2010 Proceedings of ESSCIRC.

A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

Suki Kim, Soo-In Cho, Jung-Hwan Choi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Bidirectional IO Using a 500MHz Clock for High-Speed Memory

Suki Kim, Soo-In Cho, Jung-Hwan Choi, 2004 .

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

Soo-In Cho, Jung-Hwan Choi, Byung-Chul Kim, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

Soo-In Cho, Jung-Hwan Choi, In-Young Chung, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

Jin-Hyun Kim, Hong-Sun Hwang, Woo-Seop Kim, 2005, IEEE J. Solid State Circuits.