Yeong-Jar Chang

发表

A parallel built-in diagnostic scheme for multiple embedded memories

Cheng-Wen Wu, Li-Ming Denq, Wen Ching Wu, 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

Synthesis of multi-variable MVL functions using hybrid mode CMOS logic

Chung-Len Lee, Yeong-Jar Chang, 1994, Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94).

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Fail pattern identification for memory built-in self-repair

Cheng-Wen Wu, Chin-Lung Su, Kun-Lun Luo, 2004, 13th Asian Test Symposium.

Intelligent Policy Selection for GPU Warp Scheduler

Lih-Yih Chiou, Yeong-Jar Chang, Tsung-Han Yang, 2019, 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

A parallel built-in self-diagnosis scheme for embedded memory

Rei-Fu Huang, Yeong-Jar Chang, Cheng-Wen Wu, 2003 .

MRAM defect analysis and fault modeling

Cheng-Wen Wu, Chin-Lung Su, Ming-Jer Kao, 2004, 2004 International Conferce on Test.

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, J. Inf. Sci. Eng..

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle

Chung-Len Lee, Wen Ching Wu, Yeong-Jar Chang, 2005, 14th Asian Test Symposium (ATS'05).

A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models

Jai-Ming Lin, Yeong-Jar Chang, Ya-Ting Shyu, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A testable BIST design for PLL

Kun-Lun Luo, Yeong-Jar Chang, Shen-Tien Lin, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

A memory built-in self-diagnosis design with syndrome compression

Cheng-Wen Wu, Chin-Lung Su, Rei-Fu Huang, 2004, Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).

An area-efficient design for Programmable memory Built-In Self-Test

Yeong-Jar Chang, Chung-Fu Lin, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Wing-Kai Hon, Shih-Chieh Chang, Yeong-Jar Chang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

A parallel built-in diagnostic scheme for multiple embedded memories

Cheng-Wen Wu, Li-Ming Denq, Rei-Fu Huang, 2004 .

A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances

Yeong-Jar Chang, Chung-Fu Lin, Yu-Wei Chen, 2008, 2008 IEEE International Test Conference.

Embedded memory diagnostic data compression using differential address

Cheng-Wen Wu, Chin-Lung Su, Rei-Fu Huang, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Test pattern generation and clock disabling for test time and power reduction

Ji-Jan Chen, Kun-Lun Luo, Yeong-Jar Chang, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Built-in high resolution signal generator for testing ADC and DAC

Soon-Jyh Chang, Chee-Kian Ong, Yeong-Jar Chang, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Wing-Kai Hon, Shih-Chieh Chang, Yeong-Jar Chang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MRAM Defect Analysis and Fault Modeli

Cheng-Wen Wu, Chin-Lung Su, Ming-Jer Kao, 2004, ITC.

Fast Steady-State Thermal Analysis

Lih-Yih Chiou, Yeong-Jar Chang, Liang-Ying Lu, 2018, 2018 International SoC Design Conference (ISOCC).

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC

Jai-Ming Lin, Yeong-Jar Chang, Ya-Ting Shyu, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation

Jai-Ming Lin, Yeong-Jar Chang, Ya-Ting Shyu, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Reliability Physics Symposium.