B.M. Helal

A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation

B.M. Helal, M.Z. Straayer, Gu-Yeon Wei, 2007, 2007 IEEE Symposium on VLSI Circuits.

A low noise programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop

B.M. Helal, M.H. Perrott, Chun-Ming Hsu, 2009, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

B.M. Helal, M.Z. Straayer, Gu-Yeon Wei, 2008, IEEE Journal of Solid-State Circuits.