John M. Emmert

发表

Two-dimensional Placement Using Tabu Search

Dinesh K. Bhatia, John M. Emmert, 2001, VLSI Design.

Recovering faulty processing elements to enhance reliability and lifecycle in VLSI processor arrays

Charles E. Stroud, John M. Emmert, Andrew M. Taylor, 2001, 2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. No.01CH37237).

On Using Tabu Search for Design Automation of VLSI Systems

John M. Emmert, Dinesh Bhatia, Sandeep Lodha, 2003, J. Heuristics.

Fast timing driven placement using tabu search

Dinesh Bhatia, John M. Emmert, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A Fault Tolerant Technique for FPGAs

Dinesh K. Bhatia, John M. Emmert, D. Bhatia, 2000, J. Electron. Test..

A methodology for fast FPGA floorplanning

Dinesh Bhatia, John M. Emmert, 1999, FPGA '99.

Fault injection emulator for field programmable gate arrays

Charles E. Stroud, John M. Emmert, Thomas Slaughter, 2001, SPIE ITCom.

An Asynchronous MPGA THx2 Cell and Architecture for Mitigating Side-Channel Attacks

John M. Emmert, Anvesh Perumalla, 2019, 2019 IEEE National Aerospace and Electronics Conference (NAECON).

Online Fault Tolerance for FPGA Logic Blocks

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Creating Resource Agents for Collaborative Engineering Environment (CEE) Research Using the Common Object Request Broker Architecture (CORBA) Framework

Luis Concha, John M. Emmert, Diane Starkey, 2001 .

On-Line Testing and Reconfiguration of Field Programmable Gate Arrays (FPGAs) for Fault-Tolerant (FT) Applications in Adaptive Computing Systems (ACS)

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2002 .

Incremental routing in FPGAs

John M. Emmert, Dinesh Bhatia, 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

A survey of fault tolerant methodologies for FPGAs

John M. Emmert, Jason A. Cheatham, Stanley Baumgart, 2006, TODE.

A new bridging fault model for more accurate fault behavior

Charles E. Stroud, John M. Emmert, J. R. Bailey, 2000, 2000 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. Future Sustainment for Military Aerospace (Cat. No.00CH37057).

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Dinesh Bhatia, John M. Emmert, 1997, FPL.

Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, DFT.

Algorithms for physical mapping of circuits to field-programmable gate arrays

John M. Emmert, Dinesh Bhatia, 1999 .

Window rip-up for faster testing and fault tolerance in FPGAs

John M. Emmert, Andrew M. Taylor, P. Kataria, 2001, 2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. No.01CH37237).

Performance Penalty for Fault Tolerance in Roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2000, FPL.

Dynamic fault tolerance in FPGAs via partial reconfiguration

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

Bridging fault extraction from physical design data for manufacturing test development

Charles E. Stroud, Dragan Nikolic, John M. Emmert, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Online BIST and BIST-based diagnosis of FPGA logic blocks

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On-line BIST and diagnosis of FPGA interconnect using roving STARs

Charles E. Stroud, Miron Abramovici, John M. Emmert, 2001, Proceedings Seventh International On-Line Testing Workshop.

On-line incremental routing for interconnect fault tolerance in FPGAs minus the router

John M. Emmert, Jason A. Cheatham, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL

Saiyu Ren, John M. Emmert, Ray Siferd, 2011 .

An FFT approximation technique suitable for on-chip generation and analysis of sinusoidal signals

John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

A monolithic spectral BIST technique for control or test of analog or mixed-signal circuits

John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Tabu Search: Ultra-Fast Placement for FPGAs

Dinesh Bhatia, John M. Emmert, 1999, FPL.

An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks

John M. Emmert, Anvesh Perumalla, Luis Concha, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

NSF CHEST IUCRC: Case Study for Leveraging NSF IUCRCs for R&D

John M. Emmert, Anvesh Perumalla, Scott Fischer, 2019, 2019 IEEE National Aerospace and Electronics Conference (NAECON).

EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

John M. Emmert, Sara A. VanDewerker, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs

Rashmi Jha, John M. Emmert, Abhijeet Barua, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).