Holger Eisenreich

发表

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

Stephan Henker, Jens-Uwe Schluessler, René Schüffny, 2015, IEEE Journal of Solid-State Circuits.

Efficient compensation of delay variations in high-speed network-on-chip data links

René Schüffny, Dennis Walter, Sebastian Höppner, 2010, 2010 International Symposium on System on Chip.

Pulsed Multi-Layered Image Filtering: A VLSI Implementation

Stephan Henker, Rene Schuffny, Christian Mayr, 2008 .

A deep-submicron CMOS flow for general-purpose timing-detection insertion

René Schüffny, Dennis Walter, Sebastian Höppner, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

Gerhard Fettweis, Stephan Henker, René Schüffny, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM

Dennis Walter, Sebastian Höppner, Holger Eisenreich, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

Stephan Henker, Jörg Schreiter, Dennis Walter, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology

Johannes Partzsch, Christian Mayr, Dennis Walter, 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology

René Schüffny, Dennis Walter, Sebastian Höppner, 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

An MPSoC for energy-efficient database query processing

Gerhard Fettweis, Yong Chen, Stephan Henker, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Hardware Performance Monitor for Microelectronic Circuits with adaptive power control

Sebastian Höppner, Holger Eisenreich, 2013 .

A novel ADPLL design using successive approximation frequency control

Stephan Henker, René Schüffny, Christian Mayr, 2009, Microelectron. J..

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates

Gerhard Fettweis, René Schüffny, Emil Matús, 2012, 2012 IEEE International Solid-State Circuits Conference.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

Stephan Henker, René Schüffny, Dennis Walter, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

Gerhard Fettweis, Stephan Hartmann, Sebastian Hoppner, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

An open-loop clock generator for fast frequency scaling in 65nm CMOS technology

Sebastian Hoppner, Stephan Henker, Rene Schuffny, 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

René Schüffny, Sebastian Höppner, Georg Ellguth, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology

Christian Mayr, Holger Eisenreich, Florian Schraut, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC

Dennis Walter, Sebastian Höppner, Holger Eisenreich, 2019, ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC).

A heterogeneous SDR MPSoC in 28nmCMOS for low-latency wireless applications

Gerhard Fettweis, Norbert Wehn, Yong Chen, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

René Schüffny, Dennis Walter, Sebastian Höppner, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

A compact on-chip IR-drop measurement system in 28 nm CMOS technology

Stephan Henker, René Schüffny, Sebastian Höppner, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 32 GBit/s communication SoC for a waferscale neuromorphic system

Stephan Henker, René Schüffny, Johannes Partzsch, 2012, Integr..

Low power design of the X-GOLD® SDR 20 baseband processor

Jens-Uwe Schluessler, Jörg Berthold, Wolfgang Raab, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

Stephan Hartmann, Stephan Henker, Johannes Partzsch, 2011, Front. Neurosci..

Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project

Gerhard Fettweis, Corrado Carta, Frank Ellinger, 2013 .