Mohammad H. Tehranipour

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

Krishnendu Chakrabarty, Mehrdad Nourani, Mohammad H. Tehranipour, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Multiple transition model and enhanced boundary scan architecture to test interconnects for signal integrity

Mehrdad Nourani, Nisar Ahmed, Mohammad H. Tehranipour, 2003, Proceedings 21st International Conference on Computer Design.

Extending JTAG for testing signal integrity in SoCs

Mehrdad Nourani, Nisar Ahmed, Mohammad H. Tehranipour, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

Zainalabedin Navabi, Sied Mehdi Fakhraie, Mohammad H. Tehranipour, 2004, J. Electron. Test..

eUTDSP: a design study of a new VLIW-based DSP architecture

Sied Mehdi Fakhraie, Mohammad H. Tehranipour, G. R. Chaji, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

RL-huffman encoding for test compression and power reduction in scan applications

Mehrdad Nourani, Mohammad H. Tehranipour, M. Nourani, 2005, TODE.

Signal integrity loss in SoC's interconnects: a diagnosis approach using embedded microprocessor

Mehrdad Nourani, Mohammad H. Tehranipour, 2002, Proceedings. International Test Conference.

Low power pattern generation for BIST architecture

Mehrdad Nourani, Nisar Ahmed, Mohammad H. Tehranipour, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Mixed RL-Huffman encoding for power reduction and data compression in scan test

Ali Afzali-Kusha, Mehrdad Nourani, Mohammad H. Tehranipour, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Testing SoC interconnects for signal integrity using extended JTAG architecture

Mehrdad Nourani, Nisar Ahmed, Mohammad H. Tehranipour, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing SoC interconnects for signal integrity using boundary scan

Mehrdad Nourani, Nisar Ahmed, Mohammad H. Tehranipour, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Frequency driven repeater insertion for deep submicron

Mehrdad Nourani, Dian Zhou, Nisar Ahmed, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

An efficient BIST method for testing of embedded SRAMs

Zainalabedin Navabi, Sied Mehdi Fakhraie, Mohammad H. Tehranipour, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).