Tso-Bing Juang

发表

Low-error carry-free fixed-width multipliers with low-cost compensation circuits

Shen-Fu Hsiao, Tso-Bing Juang, 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications

Tso-Bing Juang, Ying-Ren Lee, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Multifunction RNS Modulo 2n ± 1 Multipliers

Jian-Hao Huang, Tso-Bing Juang, Chao-Tsung Kuo, 2012, J. Circuits Syst. Comput..

A novel VLSI iterative divider architecture for fast quotient generation

Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design

Yu Hen Hu, Shen-Fu Hsiao, Cheng-Han Lee, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Fast binary to BCD converters for decimal communications using new recoding circuits

Tso-Bing Juang, Yu-Ming Chiu, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Area-efficient 3-input decimal adders using simplified carry and sum vectors

Tso-Bing Juang, Chao-Tsung Kuo, Hsin-Hao Peng, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]

Ming-Yu Tsai, Tso-Bing Juang, Chin-Chieh Chiu, 2009, IEEE Trans. Circuits Syst. II Express Briefs.

Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems

Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin, 2018, 2018 International SoC Design Conference (ISOCC).

Low-cost concurrent error detection schemes for logarithmic converters

Tso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu, 2016, 2016 International SoC Design Conference (ISOCC).

New recoding methods for fully pipelined parallel CORDIC rotations

Tso-Bing Juang, Chin-Chieh Chiu, 2015, 2015 International SoC Design Conference (ISOCC).

50 Years of CORDIC: Algorithms, Architectures, and Applications

K. Sridharan, Koushik Maharatna, Javier Valls-Coquillat, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

High-speed binary to binary-coded-decimal converters for decimal multiplications

Tso-Bing Juang, Yu-Ming Chiu, 2013, 2013 International SoC Design Conference (ISOCC).

Low-area implementations of concurrent error detection logarithmic processors

Tso-Bing Juang, Ying-Ren Lee, 2017, 2017 International SoC Design Conference (ISOCC).

Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

Ming-Yu Tsai, Tso-Bing Juang, Chin-Chieh Chiu, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A high performance function generator for multiplier-based arithmetic operations

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Para-CORDIC: parallel CORDIC rotation algorithm

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

Tso-Bing Juang, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2005, IEICE Trans. Inf. Syst..

Area-efficient parallel-prefix Ling adders

Pramod Kumar Meher, Tso-Bing Juang, Chung-Chun Kuan, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations

Yu Hen Hu, Shen-Fu Hsiao, Tso-Bing Juang, 2004, IEEE Signal Process. Lett..

A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding

Tso-Bing Juang, Jian-Hao Huang, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Discussions on the CORDIC processor using leading zeros detector

Shen-Fu Hsiao, Tso-Bing Juang, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations

Tso-Bing Juang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders

Tso-Bing Juang, Han-Lung Kuo, Hsin-Hao Peng, 2012, 2012 International SoC Design Conference (ISOCC).

Partition methodology for the final adder in a tree-structure parallel multiplier generator

Shen-Fu Hsiao, Ming-Yu Tsai, Tso-Bing Juang, 2002, Asia-Pacific Conference on Circuits and Systems.

Lower-Error Antilogarithmic Converters Using Binary Error Searching Schemes

Tso-Bing Juang, Chao-Tsung Kuo, 2013 .

A lower error antilogarithmic converter using novel four-region piecewise-linear approximation

Tso-Bing Juang, Chao-Tsung Kuo, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Area/Delay Efficient Recoding Methods for Parallel

Tso-Bing Juang, Cordic Rotations, 2006 .

Area-saving technique for low-error redundant binary fixed-width multiplier implementation

Chip-Hong Chang, Tso-Bing Juang, Chi-Chung Wei, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.