Sriram R. Vangal

发表

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2011, IEEE Journal of Solid-State Circuits.

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Hong Wang, Deepak Mathaikutty, Sriram R. Vangal, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Test implications and challenges in near threshold computing special session

Mehdi Baradaran Tahoori, Robert C. Aitken, Sriram R. Vangal, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Chapter 2 On-Chip Networks for Multicore Systems

Sriram R. Vangal, Li-Shiuan Peh, Stephen W. Keckler, 2017 .

Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures

Sriram R. Vangal, S. Vangal, 2006 .

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 5-GHz Mesh Interconnect for a Teraflops Processor

Sriram R. Vangal, Nitin Borkar, Shekhar Y. Borkar, 2007, IEEE Micro.

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003, IEEE J. Solid State Circuits.

Techniques for robust communication

Sriram R. Vangal, Somnath Paul, Michael D. Abbott, 2013 .

A 2 Tb/s 6$\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Sriram R. Vangal, Shasi Kumar, Tiju Jacob, 2011, IEEE Journal of Solid-State Circuits.

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Amit Agarwal, Ram Krishnamurthy, Sriram R. Vangal, 2020 .

Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies

Partha Pratim Pande, Sriram R. Vangal, 2010, IEEE Des. Test Comput..

5-GHz 32-bit Integer Execution Core in 130-nm Dual-VT CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2001 .

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2002 .

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Saurabh Dighe, Sriram R. Vangal, Tiju Jacob, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2010, 2010 23rd International Conference on VLSI Design.

A high-speed, multithreaded TCP offload engine for 10 Gb/s ethernet

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2005 .

Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)

Sriram R. Vangal, Pedram Mohseni, 2019, IEEE J. Solid State Circuits.

A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor

Sriram R. Vangal, Vivek De, Shailendra Jain, 2014, 2014 IEEE International Conference on IC Design & Technology.

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Saurabh Dighe, Sriram R. Vangal, Vasantha Erraguntla, 2011, IEEE Journal of Solid-State Circuits.

Resiliency for many-core system on a chip

Sriram R. Vangal, Jason Howard, James Tschanz, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

90nm Dual VT CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003 .

A 2 Tb/s 6 × 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Sriram R. Vangal, Shasi Kumar, Tiju Jacob, 2011, VLSIC 2011.

IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS

Saurabh Dighe, Sriram R. Vangal, Shailendra Jain, 2013, IEEE Micro.

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Saurabh Dighe, Sriram R. Vangal, Jason Howard, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

The 48-core SCC Processor: the Programmer's View

Saurabh Dighe, Sriram R. Vangal, Jason Howard, 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

Sriram R. Vangal, Shasi Kumar, Vasantha Erraguntla, 2012, 2012 25th International Conference on VLSI Design.

A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

14.7 A 10GHz TCP Offload Accelerator for 10Gb/s Ethernet in 90nm Dual-VT CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003 .

Claremont: A Solar-Powered Near-Threshold Voltage IA-32 Processor

Sriram R. Vangal, Shailendra Jain, 2013 .

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

Ram Krishnamurthy, Mircea R. Stan, Sriram R. Vangal, 2002 .