Shasi Kumar

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2011, IEEE Journal of Solid-State Circuits.

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 2 Tb/s 6$\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Sriram R. Vangal, Shasi Kumar, Tiju Jacob, 2011, IEEE Journal of Solid-State Circuits.

High Speed and Low Power VLSI Architecture for Inexact Speculative Adder

Shasi Kumar, M Mahesh, 2020 .

An IA-32 processor with a wide voltage operating range in 32nm CMOS

Saurabh Dighe, Shasi Kumar, Jason Howard, 2012, 2012 IEEE Hot Chips 24 Symposium (HCS).

A 2 Tb/s 6 × 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Sriram R. Vangal, Shasi Kumar, Tiju Jacob, 2011, VLSIC 2011.

A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

Shasi Kumar, Tiju Jacob, Vasantha Erraguntla, 2010, 2010 Symposium on VLSI Circuits.

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

Sriram R. Vangal, Shasi Kumar, Vasantha Erraguntla, 2012, 2012 25th International Conference on VLSI Design.