Vivek De

发表

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2011, IEEE Journal of Solid-State Circuits.

Scaling of stack effect and its application for leakage reduction

Anantha Chandrakasan, Vivek De, Shekhar Y. Borkar, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process

Paolo A. Aseron, Jason Howard, Vivek De, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Guest editorial

Luca Benini, Vivek De, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions

Vivek De, David Stoppa, Jonathan Chang, 2015, IEEE J. Solid State Circuits.

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes

Suhwan Kim, James Tschanz, Vivek De, 2018, 2018 IEEE Symposium on VLSI Circuits.

Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

Kaushik Roy, Vivek De, Ali Keshavarzi, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Vivek De, Siva G. Narendra, James W. Tschanz, 2002, VLSIC 2002.

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

Vivek De, Xiaosen Liu, Charles Augustine, 2020, IEEE Journal of Solid-State Circuits.

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Hong Wang, Deepak Mathaikutty, Sriram R. Vangal, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

F max /V min and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS

Vivek De, Muhammad M. Khellah, James W. Tschanz, 2017, VLSIT 2017.

Monolithic DC-DC converter analysis and MOSFET gate voltage optimization

Vivek De, Eby G. Friedman, Volkan Kursun, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Reducing the data switching activity on serial link buses

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design

Lu Wang, Andrew B. Kahng, Vivek De, 2015, ACM J. Emerg. Technol. Comput. Syst..

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches

Vivek De, Dinesh Somasekhar, Yibin Ye, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

James Tschanz, Vivek De, Shekhar Y. Borkar, 2002, DAC '02.

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study

Vivek De, Monodeep Kar, Saibal Mukhopadhyay, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Statistical estimation of correlated leakage power variation and its application to leakage-aware design

Abhijit Chatterjee, Adit D. Singh, Vivek De, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2010, IEEE Custom Integrated Circuits Conference 2010.

Foreword: Welcome to the 2013 Symposium on VLSI Circuits

Vivek De, Hideyuki Kabuo, 2013, 2013 Symposium on VLSI Circuits.

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

Keith A. Bowman, James Tschanz, Vivek De, 2013, IEEE Journal of Solid-State Circuits.

An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop

Vivek De, Suyoung Bang, Pascal Meinerzhagen, 2020, IEEE Journal of Solid-State Circuits.

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

Sanu Mathew, Vivek De, Monodeep Kar, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

James Tschanz, Vivek De, Kaushik Mazumdar, 2016, IEEE Journal of Solid-State Circuits.

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

F1: Intelligent energy-efficient systems at the edge of IoT

James Myers, Dennis Sylvester, Ingrid Verbauwhede, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Low voltage low power CMOS design techniques for deep submicron ICs

Kaushik Roy, Vivek De, Liqiong Wei, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

A fully-digital phase-locked low dropout regulator in 32nm CMOS

James Tschanz, Vivek De, Arijit Raychowdhury, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities

Sanu Mathew, Vivek De, Monodeep Kar, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/

Kaushik Roy, Vivek De, Ali Keshavarzi, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Variations-aware low-power design with voltage scaling

Vivek De, Farid N. Najm, Muhammad M. Khellah, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002

Mary Jane Irwin, Ingrid Verbauwhede, Vivek De, 2002, ISLPED.

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Keith A. Bowman, Vivek De, Ali Keshavarzi, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

Vivek De, Farid N. Najm, Muhammad M. Khellah, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

Kevin Zhang, Vivek De, Shekhar Borkar, 2000, ISLPED '00.

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

Vivek De, A. Chatterjee, P. Pant, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

Vivek De, Saibal Mukhopadhyay, Monodeep Kar, 2020, IEEE Journal of Solid-State Circuits.

Monolithic voltage conversion in low-voltage CMOS technologies

Vivek De, Eby G. Friedman, Volkan Kursun, 2005, Microelectron. J..

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

Sanu Mathew, Vivek De, Monodeep Kar, 2017, J. Hardw. Syst. Secur..

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Amit Agarwal, Ram Krishnamurthy, Sriram R. Vangal, 2020 .

Serial-link bus: a low-power on-chip bus architecture

Vivek De, Yehea Ismail, Muhammad M. Khellah, 2005, ICCAD 2005.

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Technology and design challenges for low power and high performance [microprocessors]

Vivek De, Shekhar Y. Borkar, S. Borkar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

A dual-Vt layout approach for statistical leakage variability minimization in nanometer CMOS

Abhijit Chatterjee, Adit D. Singh, Vivek De, 2005, 2005 International Conference on Computer Design.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Vivek De, Volkan Kursun, Siva G. Narendra, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS

Vivek De, 2013, ASYNC.

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS

James Tschanz, Vivek De, Arijit Raychowdhury, 2013, IEEE Journal of Solid-State Circuits.

Near-threshold voltage design in nanoscale CMOS

Vivek De, 2013, DATE '13.

Design optimizations microprocessors at low temperature

Vivek De, Siva G. Narendra, Ali Keshavarzi, 2004, Proceedings. 41st Design Automation Conference, 2004..

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response

James Tschanz, Vivek De, Xiaosen Liu, 2019, 2019 Symposium on VLSI Circuits.

Reducing the data switching activity of serialized datastreams

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Cascode buffer for monolithic voltage conversion operating at high input supply voltages

Vivek De, Eby G. Friedman, Volkan Kursun, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Vivek De, J. Tschanz, S. Narendra, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Leakage and process variation effects in current testing on future CMOS circuits

Kaushik Roy, James Tschanz, Vivek De, 2002, IEEE Design & Test of Computers.

Sub-90 nm technologies-challenges and opportunities for CAD

Vivek De, Shekhar Y. Borkar, Tanay Karnik, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

A Digital Low-Dropout Regulator With Autotuned PID Compensator and Dynamic Gain Control for Improved Transient Performance Under Process Variations and Aging

Vivek De, Saibal Mukhopadhyay, Monodeep Kar, 2020, IEEE Transactions on Power Electronics.

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

Kaustav Banerjee, Vivek De, Hamed F. Dadgour, 2008, ICCAD 2008.

14.7 A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation

James Tschanz, Vivek De, Xiaosen Liu, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Serial-link bus: a low-power on-chip bus architecture

Yehea I. Ismail, James Tschanz, Vivek De, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Analytical Model for the Propagation Delay of Through Silicon Vias

Yehea I. Ismail, Vivek De, DiaaEldin Khalil, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Dynamic noise analysis in precharge-evaluate circuits

Kaushik Roy, Vivek De, Dinesh Somasekhar, 2000, Proceedings 37th Design Automation Conference.

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator pdf

Sanu Mathew, Vivek De, Raheem A. Beyah, 2018, ArXiv.

Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits

Vivek De, Makoto Nagata, 2012, IEEE J. Solid State Circuits.

25.3 A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator

Sanu Mathew, Vivek De, Monodeep Kar, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Design for test and reliability in ultimate CMOS

Yervant Zorian, Nacer-Eddine Zergainoh, Lorena Anghel, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power

James Tschanz, Vivek De, Siva G. Narendra, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Resilient microprocessor design for high performance & energy efficiency

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Evening Panel Discussion: Process Variation: Is It Too Much to Handle?

Vivek De, Ron Wilson, Siva G. Narendra, 2002, ISQED.

2.4 A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots

Vinayak Honkote, Paolo A. Aseron, Vivek De, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

Abhijit Chatterjee, Vivek De, Pankaj Pant, 1997, DAC.

Energy efficient designs with wide dynamic range

Vivek De, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

8.1 A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging

James Tschanz, Vivek De, Krishnan Ravichandran, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

Vivek De, Eby G. Friedman, Volkan Kursun, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Statistical modeling of metal-gate Work-Function Variability in emerging device technologies and implications for circuit design

Kaustav Banerjee, Vivek De, Hamed F. Dadgour, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2007, VLSI Design.

What does ultra low power requirements mean for side-channel secure cryptography?

Vivek De, Monodeep Kar, Saibal Mukhopadhyay, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Energy-Efficient Computing in Nanoscale CMOS

Vivek De, 2016, IEEE Design & Test.

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

Vivek De, Eby G. Friedman, Volkan Kursun, 2005 .

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses

Yehea I. Ismail, James Tschanz, Vivek De, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays

Keith A. Bowman, James Tschanz, Vivek De, 2011, IEEE Journal of Solid-State Circuits.

A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming

Vivek De, Harish Kumar Krishnamurthy, Tarun Mahajan, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

Proceedings of the 15th ACM Great Lakes symposium on VLSI

Vivek De, Kanad Ghose, Peter M. Kogge, 2005, ACM Great Lakes Symposium on VLSI.

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

Kaushik Roy, Vivek De, Shekhar Y. Borkar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Exploiting on-chip power management for side-channel security

Sanu Mathew, Vivek De, Monodeep Kar, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Circuits for resilient systems

Vivek De, 2013, FTXS '13.

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache

Kevin Zhang, Vivek De, Shekhar Borkar, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Mark C. Johnson, Kaushik Roy, Vivek De, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Challenges in Nanometric Technology Scaling: Trends and Projections

Vivek De, Ali Keshavarzi, Jaume Segura, 2002, VTS.

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Time-Borrowing Multi-Cycle On-Chip Interconnects for Delay Variation Tolerance

Yehea I. Ismail, Keith A. Bowman, James Tschanz, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays

Vivek De, Jaydeep P. Kulkarni, Tanay Karnik, 2010, IEEE Custom Integrated Circuits Conference 2010.

Energy Efficient Volatile Memory Circuits for the IoT Era

Vivek De, Jaydeep P. Kulkarni, James W. Tschanz, 2017 .

Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits

Nitin Borkar, Vivek De, Fatih Hamzaoglu, 2009, IEEE Journal of Solid-State Circuits.

Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Anantha Chandrakasan, Vivek De, Shekhar Y. Borkar, 2002, ISLPED '02.

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

James Tschanz, Vivek De, Shekhar Y. Borkar, 2001, ISLPED '01.

Low-voltage-swing monolithic dc-dc conversion

Vivek De, Eby G. Friedman, Volkan Kursun, 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS

Suhwan Kim, Hong Wang, Hao Luo, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor

Sriram R. Vangal, Vivek De, Shailendra Jain, 2014, 2014 IEEE International Conference on IC Design & Technology.

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Saurabh Dighe, Sriram R. Vangal, Vasantha Erraguntla, 2011, IEEE Journal of Solid-State Circuits.

Fine-grain power management in manycore processor and System-on-Chip (SoC) designs

Vivek De, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Effects of random MOSFET parameter fluctuations on total power consumption

Vivek De, James D. Meindl, Xinghai Tang, 1996, ISLPED.

Life is CMOS: why chase the life after?

Vivek De, Shekhar Y. Borkar, George Sery, 2002, DAC '02.

Techniques for Power and Process Variation Minimization

Vivek De, Lawrence T. Clark, 2004 .

Active Leakage Reduction and Multi-Performance Devices

Vivek De, Siva G. Narendra, James W. Tschanz, 2006 .

A 22nm dynamically adaptive clock distribution for voltage droop tolerance

Keith A. Bowman, James Tschanz, Vivek De, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering

Sanu Mathew, Vivek De, Monodeep Kar, 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

Vivek De, Siva G. Narendra, Krishnamurthy Soumyanath, 2004 .

EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!)

Vivek De, Phillip Restle, Paul Ferguson, 2018, ISSCC.

Resiliency for many-core system on a chip

Sriram R. Vangal, Jason Howard, James Tschanz, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Total power-optimal pipelining and parallel processing under process variations in nanometer technology

Trevor N. Mudge, Keith A. Bowman, Vivek De, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

A D&T Roundtable: Challenges for Low-Power and High-Performance Chips

Ching-Te Chuang, Vivek De, Shih-Lien Lu, 1998, IEEE Des. Test Comput..

Design and optimization of low voltage high performance dual threshold CMOS circuits

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Process Variation and Adaptive Design

Anantha P. Chandrakasan, Vivek De, Siva G. Narendra, 2006 .

8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation

James Tschanz, Vivek De, Nachiket V. Desai, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Session details: Statistical optimization and manufacturability

Vivek De, Chandramouli Kashyap, Sani Nassif, 2005, DAC 2005.

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques

Yehea I. Ismail, James Tschanz, Vivek De, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS

James Tschanz, Vivek De, Muhammad M. Khellah, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001

Mary Jane Irwin, Enrico Macii, Vivek De, 2001, International Symposium on Low Power Electronics and Design.

Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits

Vivek De, Hideyuki Kabuo, 2013, IEEE J. Solid State Circuits.

Leakage-tolerant design techniques for high performance processors

Vivek De, 2002, ISPD '02.

A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS

Vivek De, Krishnan Ravichandran, Pavan Kumar, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

James Tschanz, Vivek De, Shekhar Y. Borkar, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Analysis and implications of ic cooling for deep nanometer scale cmos technologies

Kaustav Banerjee, Vivek De, Sheng-Chih Lin, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems

Marian Verhelst, Meng-Fan Chang, Jun Deguchi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A new technique for standby leakage reduction in high-performance circuits

Vivek De, Yibin Ye, Shekhar Beaverton Borkar, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

Accurate Estimation of SRAM Dynamic Stability

Yehea I. Ismail, Vivek De, Nam-Sung Kim, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

F1: Designing secure systems: Manufacturing, circuits and architectures

Marian Verhelst, Yusuf Leblebici, Vivek De, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies

Vivek De, Michael T. Niemier, Xiaobo Sharon Hu, 2019, IEEE Des. Test.

Comparative Analysis of Conventional and Statistical Design Techniques

Keith A. Bowman, James Tschanz, Vivek De, 2007, 2007 44th ACM/IEEE Design Automation Conference.

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)

Vivek De, James D. Meindl, J. Meindl, 1996, Proceedings / International Symposium on Low Power Electronics and Design.

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging

Paolo A. Aseron, James Tschanz, Vivek De, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Circuit techniques for dynamic variation tolerance

Keith A. Bowman, James Tschanz, Vivek De, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

Vivek De, Krishnan Ravichandran, Pavan Kumar, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

Low power and high performance design challenges in future technologies

Vivek De, Shekhar Y. Borkar, 2000, ACM Great Lakes Symposium on VLSI.

Sub-90nm technologies: challenges and opportunities for CAD

Vivek De, Shekhar Borkar, Tanay Karnik, 2002, ICCAD 2002.

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines

Vivek De, Monodeep Kar, Saibal Mukhopadhyay, 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Resilient design in scaled CMOS for energy efficiency

Keith A. Bowman, James Tschanz, Vivek De, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping

Paolo A. Aseron, James Tschanz, Vivek De, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Circuit techniques for low-power CMOS GSI

Vivek De, Azeez J. Bhavnagarwala, Blanca Austin, 1996, ISLPED '96.

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core

James Tschanz, Vivek De, Muhammad M. Khellah, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based

Massimo Alioto, Vivek De, Andrea Marongiu, 2018, IEEE J. Emerg. Sel. Topics Circuits Syst..

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2011, IEEE Journal of Solid-State Circuits.

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation

Vivek De, Siva G. Narendra, Stephen Tang, 2003, ISLPED '03.

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Saurabh Dighe, Sriram R. Vangal, Jason Howard, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

Sanu Mathew, Vivek De, Monodeep Kar, 2016, ISLPED.

Design and reliability challenges in nanometer technologies

Vivek De, Shekhar Y. Borkar, Tanay Karnik, 2004, Proceedings. 41st Design Automation Conference, 2004..

SRAM dynamic stability estimation using MPFP and its applications

Yehea I. Ismail, Vivek De, Nam-Sung Kim, 2009, Microelectron. J..

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging

Paolo A. Aseron, James Tschanz, Vivek De, 2016, IEEE Journal of Solid-State Circuits.

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Formal derivation of optimal active shielding for low-power on-chip buses

Yehea I. Ismail, James Tschanz, Vivek De, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities

Vivek De, 2018, NOCS.

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Vivek De, Shekhar Y. Borkar, Siva G. Narendra, 2001, ISLPED '01.

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS

James Tschanz, Vivek De, Arijit Raychowdhury, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Parameter variations and impact on circuits and microarchitecture

James Tschanz, Vivek De, Shekhar Y. Borkar, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Best practices in low-power design. 2. Industrial power reduction experiences [Tutorial 4]

Vivek De, R. Zafalon, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Adaptive and Resilient Circuits for Dynamic Variation Tolerance

Keith A. Bowman, James Tschanz, Vivek De, 2013, IEEE Design & Test.

Compiler support for reducing leakage energy consumption

Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Kaushik Roy, Vivek De, Liqiong Wei, 1999, DAC '99.

Variation-tolerant circuits: circuit solutions and techniques

Keith A. Bowman, James Tschanz, Vivek De, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS

James Tschanz, Vivek De, Krishnan Ravichandran, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Technology and design challenges for low power and high performance [microprocessors]

Vivek De, Shekhar Beaverton Borkar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

Keith A. Bowman, James Tschanz, Vivek De, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Energy efficient computing in nanoscale CMOS: Challenges and opportunities

Vivek De, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS

Vivek De, Monodeep Kar, Saibal Mukhopadhyay, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

PVT-variations and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits

Kevin Zhang, Vivek De, M. Khellah, 2008, 2008 IEEE Symposium on VLSI Circuits.

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

James Tschanz, Vivek De, Kaushik Mazumdar, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Leakage Dependence on Input Vector

Anantha P. Chandrakasan, Vivek De, Siva G. Narendra, 2006 .

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2017, IEEE Journal of Solid-State Circuits.

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

Yehea I. Ismail, James Tschanz, Vivek De, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Forward body bias for microprocessors in 130nm technology generation and beyond

Vivek De, Siva G. Narendra, Shekhar Beaverton Borkar, 2002, VLSIC 2002.

A 6GHz, l6Kbytes L1 Cache in a lOOnm Dual-VT Technology Using a Bitline Leakage Reduction (BLR) Technigue

Vivek De, Dinesh Somasekhar, A. Farhang, 2002 .

Intrinsic MOSFET parameter fluctuations due to random dopant placement

Vivek De, James D. Meindl, Xinghai Tang, 1997, IEEE Trans. Very Large Scale Integr. Syst..

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

James Tschanz, Vivek De, Krishnan Ravichandran, 2015, IEEE Journal of Solid-State Circuits.

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers

James Tschanz, Vivek De, Harish Krishnamurthy, 2021, 2021 Symposium on VLSI Circuits.

A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction

James Tschanz, Vivek De, Xiaosen Liu, 2021, 2021 Symposium on VLSI Circuits.

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning

Vivek De, Xiaosen Liu, Christopher Schaef, 2021, IEEE Journal of Solid-State Circuits.

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2021, IEEE Journal of Solid-State Circuits.

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation

Vivek De, Arijit Raychowdhury, Carlos Tokunaga, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation

Vivek De, Santosh Ghosh, Josef Danial, 2022, IEEE Journal of Solid-State Circuits.

A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors

James Tschanz, Vivek De, Han Wui Then, 2021, 2021 Symposium on VLSI Circuits.

36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control

Vivek De, Shreyas Sen, Santosh Ghosh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing

James Tschanz, Vivek De, Xiaosen Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

Amit Agarwal, Steven Hsu, Ram Krishnamurthy, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Full-chip subthreshold leakage power prediction model for sub-0 . 18 m CMOS

Anantha Chandrakasan, Vivek De, Shekhar Borkar, 2002 .

An All-Digital, $V$ MAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

James Tschanz, Vivek De, Suyoung Bang, 2019, IEEE Solid-State Circuits Letters.

Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic Networks

Vivek De, A. Chatterjee, P. Pant, 1997, Proceedings of the 34th Design Automation Conference.

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

Ram Krishnamurthy, Mircea R. Stan, Sriram R. Vangal, 2002 .