Hsin-Chou Chi

发表

Symmetric Crossbar Arbiters for

Yuval Tamir, Hsin-Chou Chi, 1993 .

Efficient Switches for Network-on-Chip Based Embedded Systems

Chia-Ming Wu, Hsin-Chou Chi, Hsin-Chou Chi, 2005, EUC.

Design and Implementation of Fair Queueing Algorithms for Packet Switches

Chia-Ming Wu, Hsin-Chou Chi, Wen-Pin Hsu, 2007 .

Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks

Chia-Ming Wu, Hsin-Chou Chi, Tat-Seng Chang, 2010, SIES.

Design of a multicast router for network-on-chip architectures with irregular topologies

Hsin-Chou Chi, Zhi-Hong Ye, Hsi-Che Tseng, 2015 .

Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores

Hsin-Chou Chi, Yu-Chen Hsieh, Jr-Fen Ferng, 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

Decomposed arbiters for large crossbars with multi-queue input buffers

Yuval Tamir, Hsin-Chou Chi, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Design of timing-error-resilient systolic arrays for matrix multiplication

Kun-Lin Tsai, Hsin-Chou Chi, Hsi-Che Tseng, 2011, 2011 International SoC Design Conference.

Design and implementation of a routing switch for on-chip interconnection networks

Hsin-Chou Chi, Jia-Hung Chen, Hsin-Chou Chi, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A Wrapper for Low-Power Error-Correcting Data Delivery in On-Chip Networks

Chia-Ming Wu, Hsin-Chou Chi, Ying-Ming Huang, 2006, 2006 International Conference on Communications, Circuits and Systems.

A Switch Supporting Circuit and Packet Switching for On-Chip Networks

Chia-Ming Wu, Hsin-Chou Chi, Sung-Tze Wu, 2006, DDECS.

Efficient Diagnosis of Scan Chains with Single Stuck-at Faults

Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang, 2009, 2009 International Conference on Computing, Engineering and Information.

Starvation prevention for arbiters of crossbars with multi-queue input buffers

Yuval Tamir, Hsin-Chou Chi, Y. Tamir, 1994, Proceedings of COMPCON '94.

Efficient Diagnosis of Scan Chains with Single Stuck-at Faults

Hsin-Chou Chi, Chih-Ling Yang, His-Che Tseng, 2009 .

A high-performance VLSI architecture for variable block size motion estimation

Hsin-Chou Chi, Hsi-Che Tseng, Han-Sheng Liu, 2014, 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE).

Design and implementation of a routing switch for irregular interconnection networks

Chia-Ming Wu, Hsin-Chou Chi, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Efficient IP Routing Lookups for High-Performance Routers

Chia-Ming Wu, Hsin-Chou Chi, Sheng-Chin Hsu, 2013 .

Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology

Hsin-Chou Chi, Yu-Hong Jhang, Wen-Shu Chen, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Crossbar arbitration in interconnection networks for multiprocessors and multicomputers

Hsin-Chou Chi, 1994 .

Design of a High-Performance Switch for Circuit-Switched On-Chip Networks

Chia-Ming Wu, Hsin-Chou Chi, Hsin-Chou Chi, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Reconfigurable VLSI digital filters for tolerating multiple timing errors

Hsin-Chou Chi, Hsi-Che Tseng, Chia-Wei Jeng, 2013, 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE).

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Ruay-Shiung Chang, Chia-Ming Wu, Hsin-Chou Chi, 2009 .

An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures

Chia-Ming Wu, Hsin-Chou Chi, Hsin-Chou Chi, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures

Chia-Ming Wu, Jun-Hui Lee, Hsin-Chou Chi, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Design and implementation of an IP wrapper for an on-chip network

Chia-Ming Wu, Hsin-Chou Chi, Yu-Seng Lin, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Efficient diagnosable design of the IEEE P1500 architecture for SoC testing

Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang, 2011, 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications.

Routing tree construction for interconnection networks with irregular topologies

Hsin-Chou Chi, Wen-Jen Wu, Hsin-Chou Chi, 2003, Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003. Proceedings..

Mapping of IP cores to network-on-chip architectures based on communication task graphs

Chia-Ming Wu, Hsin-Chou Chi, Ming-Chao Lee, 2005, 2005 6th International Conference on ASIC.

A High-Performance Programmable Scheduling Engine for ATM Switches

Chia-Ming Wu, Hsin-Chou Chi, Kuo-Yao Fu, 2007 .

A deadlock-free routing scheme for interconnection networks with irregular topologies

Hsin-Chou Chi, Chih-Tsung Tang, Hsin-Chou Chi, 1997, Proceedings 1997 International Conference on Parallel and Distributed Systems.