Keh-Jeng Chang

发表

A proposal for accurately modeling frequency-dependent on-chip interconnect impedance

Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Buffer Insertion Location Optimization for Post Route Optimization

Keh-Jeng Chang, Jimmy S. Wang, 2005 .

SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?

Keh-Jeng Chang, Christophe J. Bianchi, Martin G. Walker, 1999, VLSI.

A method of computer-aided design for multi-layer technologies compounds

Keh-Jeng Chang, Soo-Young Oh, Keunmyung Lee, 1993 .

Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Duane S. Boning, J. E. Chung, Keh-Jeng Chang, 1995, Proceedings of International Electron Devices Meeting.

Interconnect modeling and design in high-speed VLSI/ULSI systems

Ken Lee, Keh-Jeng Chang, Norman Chang, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Use of short-loop electrical measurements for yield improvement

Costas J. Spanos, Duane S. Boning, J. E. Chung, 1995 .

2001 needs for multi-level interconnect technology

Keh-Jeng Chang, Soo-Young Oh, Keh-Jeng Chang, 1995 .

Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

Keh-Jeng Chang, Soo-Young Oh, Norman H. Chang, 1992 .

HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects

Li-Fu Chang, Keh-Jeng Chang, Robert Mathews, 2000, ISPD '00.

Accurate on-chip variation modeling to achieve design for manufacturability

Keh-Jeng Chang, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

Incorporating process induced effects into RC extraction

Li-Fu Chang, Keh-Jeng Chang, Robert Mathews, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Tutorial C4: Title: RLCK Extraction and Simulation in High-Speed SoC Designs

Keh-Jeng Chang, 2002 .

Technological limitations in submicron on-chip interconnect

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1993, Other Conferences.

IPDA: interconnect performance design assistant

Ken Lee, Keh-Jeng Chang, Soo-Young Oh, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

Fook-Luen Heng, Andrew B. Kahng, Vijay Pitchumani, 2005, ASP-DAC.

Nondestructive Multilevel Interconnect Parameter Characterization For High-performance Manufacturable VLSI Technologies

Keh-Jeng Chang, Soo-Young Oh, Norman H. Chang, 1993, Symposium 1993 on VLSI Technology.

Using 3D Electromagnetic Simulation Software to Improve Design for Manufacturability for High-Speed 2-Layer PCB

Keh-Jeng Chang, Chih-Chieh Tang, 湯智捷, 2008 .

A Clustering Analysis Model for Golden Die Extractions Based on Wafer Acceptance Test at Semiconductor R&D Stage

Keh-Jeng Chang, F. L. Chen, Shyue-Shyh Lin, 2011 .

A UWB IR timed-array radar using time-shifted direct-sampling architecture

Shi-Yu Huang, Jun-Wei Huang, Jen-Ming Wu, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Optimum design sensitivity based on approximation concepts and dual methods

Lucien A. Schmit, Keh-Jeng Chang, L. Schmit, 1982 .

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

Fook-Luen Heng, Vijay Pitchumani, Don MacMillen, 2005, ASP-DAC '05.

Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

Keh-Jeng Chang, Sally Liu, Jun-Fu Huang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Accurate 3‐D capacitance extractions for advanced nanometer CMOS nodes

Ping-Hung Yuh, Keh-Jeng Chang, Shih-Hao Lee, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

Statistical metrology for interlevel dielectric thickness variation

Duane S. Boning, J. E. Chung, Keh-Jeng Chang, 1994, Advanced Lithography.

Accurate on-chip variation modeling to achieve design for manufacturability

Keh-Jeng Chang, 2004 .

Parameterized SPICE subcircuits for submicron multilevel interconnect modeling

Keh-Jeng Chang, Soo-Young Oh, Keunmyung Lee, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

Field-configurable test structure array (FC-TSA): enabling design for monitor, model and manufacturability

K.L. Young, Keh-Jeng Chang, J. Bordelon, 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

Optimum design sensitivity based on approximation concepts and dual methods

Lucien A. Schmit, Keh-Jeng Chang, 1984 .

When should on-chip inductance modeling become necessary for VLSI timing analysis?

Li-Fu Chang, Keh-Jeng Chang, Robert G. Mathews, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).