D. Hanson

A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

M. Wordeman, T. Kirihata, D. Netis, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Cyclostationarity and the cepstrum for operational modal analysis of MIMO systems—Part II: Obtaining scaled mode shapes through finite element model updating

Robert B. Randall, Jérôme Antoni, R.A.J. Ford, 2007 .