Yusuke Shuto

发表

0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

Yusuke Shuto, Satoshi Sugahara, S. Yamamoto, 2011 .

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Hideharu Amano, Kimiyoshi Usami, Yusuke Shuto, 2018, 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2015, 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2016, 2016 International Conference on Microelectronic Test Structures (ICMTS).

Nonvolatile static random access memory based on spin-transistor architecture

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2009 .

Energy performance of nonvolatile power-gating SRAM using SOTB technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service

Yusuke Shuto, Satoshi Sugahara, M. Tanaka, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Design of a new piezoelectronic transistor and its device and circuit performances

Yusuke Shuto, Satoshi Sugahara, Minoru Kurosawa, 2018 .

Energy performance of nonvolatile power-gating SRAM using SOTB technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Design and implementation of nonvolatile power-gating SRAM using SOTB technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2016, ISLPED.

Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2009, 2009 IEEE Custom Integrated Circuits Conference.

FinFET-based pseudo-spin-transistor: Design and performance

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2013, 2013 International Semiconductor Conference Dresden - Grenoble (ISCDG).

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops

Hideharu Amano, Kimiyoshi Usami, Yusuke Shuto, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Analysis of break-even time for nonvolatile SRAM with SOTB technology

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

Nonvolatile Static Random Access Memory Using Resistive Switching Devices: Variable-Transconductance Metal–Oxide–Semiconductor Field-Effect-Transistor Approach

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2010 .

Epitaxial Growth and Magnetic Properties of Ferromagnetic Semiconductor Ge1-xFex Thin Films Epitaxially Grown on Si(001) Substrates

Yusuke Shuto, Satoshi Sugahara, Y. Shuto, 2008 .

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2012 .

A New Spin-Functional Metal–Oxide–Semiconductor Field-Effect Transistor Based on Magnetic Tunnel Junction Technology: Pseudo-Spin-MOSFET

Yusuke Shuto, Shuu'ichirou Yamamoto, Koichiro Inomata, 2010 .

110) Ultrathin GOI layers fabricated by Ge condensation method

Mitsuru Takenaka, Shinichi Takagi, Yusuke Shuto, 2008 .

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2013 .

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2012 .

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

Yusuke Shuto, Satoshi Sugahara, Seiji Mitani, 2014 .

Spin‐Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems

Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, 2016 .