Byung Yong Choi

发表

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

Myounggon Kang, Yeong-Taek Lee, Youngsun Song, 2009 .

Programmable virtual source/drain MOSFETs

Hyungcheol Shin, Il Han Park, Chilhee Chung, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

Woo Young Choi, Byung-Gook Park, Byung Yong Choi, 2003 .

Reliable 2-bit/cell NVM technology using twin SONOS memory transistor

Byeoung-Soo Park, Byung Yong Choi, Dong Woon Kim, 2005 .

A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology

Chilhee Chung, Byung-Gook Park, Jong Duk Lee, 2004 .

A new linearity measurement algorithm for sub-micron microwave cmos

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

Byung-Gook Park, Jong Duk Lee, Byung Yong Choi, 2002 .

Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs

Woo Young Choi, Young Jin Choi, Byung Yong Choi, 2001 .

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

Yeong-Taek Lee, Kinam Kim, Ki-Tae Park, 2008, IEEE Journal of Solid-State Circuits.

Seat Common Frame Design Optimization

Sangdo Park, Byung Yong Choi, Dongwoo Jeong, 2010 .

Low Voltage Program/Erase Characteristics of Si Nanocrystal Memory with Damascene Gate FinFET on Bulk Si Wafer

Donggun Park, Byung-Il Ryu, Eun Suk Cho, 2006 .

30 nm self-aligned FinFET with large source/drain fan-out structure

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2003 .

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2002 .

25nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure

Byung-Gook Park, Donggun Park, Young June Park, 2005, 2005 International Semiconductor Device Research Symposium.

80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Byung-Gook Park, Young June Park, Byung Yong Choi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Byung-Gook Park, Chang Woo Oh, Sung Hwan Kim, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2002 .

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

Seung Beom Kim, Donggun Park, Byung-Il Ryu, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Stable extraction of linearity (V/sub IP3/) for nanoscale RF CMOS devices

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2004 .

A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2004, Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC..

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Chang Woo Oh, Donggun Park, Eun Suk Cho, 2006 .

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

Seung Beom Kim, Donggun Park, Byung-Il Ryu, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..