Nathalie Drach-Temam

发表

NUMA-aware scheduling and memory allocation for data-flow task-parallel applications

Karine Heydemann, Albert Cohen, Antoniu Pop, 2016, PPoPP.

Low-cost fault tolerance on the ALU in simple pipelined processors

Bruno Robisson, Nathalie Drach-Temam, Nguyen Minh Huu, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Automatic Detection of Performance Anomalies in Task-Parallel Programs pdf

Karine Heydemann, Albert Cohen, Antoniu Pop, 2014, ArXiv.

A Parallel Algorithm for 3D Geometry Transformations in OpenGL

Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam, 1999, Euro-Par.

Software assistance for data caches

Olivier Temam, Nathalie Drach-Temam, 1995, Future Gener. Comput. Syst..

About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors

André Seznec, Nathalie Drach-Temam, Alain Gefflaut, 1995, Parallel Process. Lett..

Evaluation of the Time-Redundant Fault Tolerance on the ALU for Simple Pipelined Processor

Bruno Robisson, Nathalie Drach-Temam, Michel Agoyan, 2009 .

Increasing hardware data prefetching performance using the second-level cache

Jean-Luc Béchennec, Nathalie Drach-Temam, Olivier Temam, 2002, J. Syst. Archit..

Architecture optimization for multimedia application exploiting data and thread-level parallelism

Alexis Vartanian, Nathalie Drach-Temam, Julien Sébot, 2005, J. Syst. Archit..

Software assistance for data caches

Olivier Temam, Nathalie Drach-Temam, 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines

André Seznec, Nathalie Drach-Temam, André Seznec, 1993, Proceedings of the 26th Annual International Symposium on Microarchitecture.

Algorithme d'ordonnancement dynamique pour exécution statique

Nathalie Drach-Temam, Michael Dupré, 2003, Tech. Sci. Informatiques.

Using Runtime Activity to Dynamically Filter Out Inefficient Data Prefetches

Karine Heydemann, Nathalie Drach-Temam, Oussama Gamoudi, 2011, Euro-Par.

Memory Bandwidth: The True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor

Nathalie Drach-Temam, Julien Sébot, 2001, Euro-Par.

Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages

Karine Heydemann, Albert Cohen, Antoniu Pop, 2014, ACM Trans. Archit. Code Optim..

Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor

Alexis Vartanian, Nathalie Drach-Temam, Julien Sébot, 2001, ICS '01.

Scalable task parallelism for NUMA: A uniform abstraction for coordinated scheduling and memory management

Karine Heydemann, Albert Cohen, Antoniu Pop, 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

Direct-mapped versus set-associative pipelined caches

André Seznec, Nathalie Drach-Temam, Daniel Windheiser, 1995, PACT.

VHC: quickly building an optimizer for complex embedded architectures

Olivier Temam, Nathalie Drach-Temam, Michael Dupré, 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..

Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches

Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam, 1999, Euro-Par.

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs

Olivier Temam, Nathalie Drach-Temam, Zheng Li, 2008, 2008 Design, Automation and Test in Europe.

Semi-unified Caches

André Seznec, Nathalie Drach-Temam, André Seznec, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

The best distribution for a parallel OpenGL 3D engine with texture caches

Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam, 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

Evaluation of high performance multicache parallel texture mapping

Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam, 1998, ICS '98.

Morpheo: A high-performance processor generator for a FPGA implementation

Jean Lou Desbarbieux, Franck Wajsbürt, Nathalie Drach-Temam, 2011, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP).

Low-cost recovery for the code integrity protection in secure embedded processors

Bruno Robisson, Nathalie Drach-Temam, Nguyen Minh Huu, 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

Étude de la sensibilité aux jeux de données de la compilation itérative

Karine Heydemann, Nathalie Drach-Temam, Alexandre Coveliers, 2008, Tech. Sci. Informatiques.

An out-of-order superscalar processor on FPGA: The ReOrder Buffer design

Jean Lou Desbarbieux, Franck Wajsbürt, Nathalie Drach-Temam, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).