Spandana Rachamalla

FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware

Arun Joseph, Charles Lefurgy, Anand Haridass, 2015, 2015 28th International Conference on VLSI Design.

Virtual logic netlist: Enabling efficient RTL analysis

Arun Joseph, Rahul M. Rao, Diwesh Pandey, 2015, Sixteenth International Symposium on Quality Electronic Design.

FreqLeak: A frequency step based method for efficient leakage power characterization in a system

Arun Joseph, Charles Lefurgy, Anand Haridass, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors

Spandana Rachamalla, Arun Joseph, Shashidhar Reddy, 2019, IET Comput. Digit. Tech..

Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis

Arun Joseph, Spandana Rachamalla, Nagu Dhanwada, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

FVCAG: A framework for formal verification driven power modeling and verification

Arun Joseph, Rahul M. Rao, Pradeep Kumar Nalla, 2016, ISLPED.