Christos Vezyrtzis

发表

Voltage references for ultra-low supply voltages

Peter R. Kinget, Christos Vezyrtzis, Ed Chiang, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

Steven M. Nowick, Yannis P. Tsividis, Christos Vezyrtzis, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques

Christos Vezyrtzis, Christos Vezyrtzis, 2013 .

Direct processing of mpeg audio using companding and BFP techniques

Daniel P. W. Ellis, Yannis P. Tsividis, Christos Vezyrtzis, 2011, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Very Low Voltage (VLV) Design

Eric Cheng, Rajiv V. Joshi, Arun Paidimarri, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Across the Stack Opportunities for Deep Learning Acceleration

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2018, ISLPED.

Efficient AI System Design With Cross-Layer Approximate Computing

Swagath Venkataramani, Xiao Sun, Mingu Kang, 2020, Proceedings of the IEEE.

A Scalable Multi-TeraOPS Core for AI Training and Inference

Swagath Venkataramani, Vijayalakshmi Srinivasan, George Gristede, 2018, IEEE Solid-State Circuits Letters.

Processing of signals using level-crossing sampling

Yannis P. Tsividis, Christos Vezyrtzis, Y. Tsividis, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A statistical critical path monitor in 14nm CMOS

Keith A. Jenkins, Karthik Balakrishnan, Christos Vezyrtzis, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Resonant clock mega-mesh for the IBM z13TM

Yong Kim, Phillip Restle, Christos Vezyrtzis, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Event-Based Data Acqu isi ti on and Digi tal Signal Processing in Continuous Time

Steven M. Nowick, Yannis Tsividis, Sharvil Patil, 2018 .

26.2 Power supply noise in a 22nm z13™ microprocessor

Malcolm Allen-Ware, Alper Buyuktosunoglu, Phillip Restle, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2018, 2018 IEEE Symposium on VLSI Circuits.

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications

Steven M. Nowick, Yannis P. Tsividis, Christos Vezyrtzis, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor

Alper Buyuktosunoglu, Phillip Restle, Pierce I-Jen Chuang, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Effect of HCI degradation on the variability of MOSFETS

Keith A. Jenkins, C. Zhou, Christos Vezyrtzis, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

A flexible, clockless digital filter

Steven M. Nowick, Yannis Tsividis, Christos Vezyrtzis, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

IBM z14 design methodology enhancements in the 14-nm technology node

José Luis Neves, Alper Buyuktosunoglu, Ofer Geva, 2018, IBM J. Res. Dev..

A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate

Steven M. Nowick, Yannis P. Tsividis, Weiwei Jiang, 2014, IEEE Journal of Solid-State Circuits.

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection

Phillip Restle, Michael S. Floyd, Christos Vezyrtzis, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).