Burhan Khurshid

发表

LUT Based Generalized Parallel Counters for State - of - art FPGAs

Burhan Khurshid, 2017 .

An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs

Burhan Khurshid, Roohie Naaz Mir, Burhan Khurshid, 2017, Circuits Syst. Signal Process..

A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique

Burhan Khurshid, Roohie Naaz Mir, Liyaqat Nazir, 2015, 2015 Annual IEEE India Conference (INDICON).

Power efficient implementation of bit-parallel unrolled CORDIC structures for FPGA platforms

Burhan Khurshid, Roohie Naaz Mir, Burhan Khurshid, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Burhan Khurshid, Roohie Naaz Mir, 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms

Burhan Khurshid, Roohie Naaz Mir, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

A High Speed 32-bit FPGA based CORDIC Architecture for Sine and Cosine Function Evaluation

Burhan Khurshid, Roohie Naz Mir, Hakim Najeeb-uddin Shah, 2013 .

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Burhan Khurshid, Roohie Naaz Mir, 2015, Int. J. Reconfigurable Comput..

Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

Burhan Khurshid, Roohie Naaz Mir, 2015 .

High Efficiency Generalized Parallel Counters for Xilinx FPGAs

Burhan Khurshid, Roohie Naaz Mir, 2015, 2015 IEEE 22nd International Conference on High Performance Computing (HiPC).

Improving synthesis of fixed-point adders on FPGAs using primitive instantiations

Burhan Khurshid, Roohie Naaz, 2015, 2015 Annual IEEE India Conference (INDICON).

Technology - Dependent Optimization of FIR Filters based on Carry - Save Multiplier and 4:2 Compressor unit

Burhan Khurshid, Roohie Naaz, 2017 .

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs

Burhan Khurshid, Roohie Naaz Mir, 2017, J. Circuits Syst. Comput..

Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs

Burhan Khurshid, 2017, J. Signal Process. Syst..

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs

Burhan Khurshid, 2017, Des. Autom. Embed. Syst..

A hybrid-radix approach for efficient implementation of unfolded CORDIC architectures for FPGA platforms

Burhan Khurshid, Animesh Kumar, Roohie Naz Mir, 2014, 2014 International Conference on Signal Processing and Integrated Networks (SPIN).

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs

Burhan Khurshid, 2018, J. Circuits Syst. Comput..

Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations

Burhan Khurshid, Roohie Naaz, 2015 .

Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Burhan Khurshid, Roohie Naaz Mir, Liyaqat Nazir, 2015 .