D. D. Tang

发表

High-speed low-power direct-coupled complementary push-pull ECL circuit

Ching-Te Chuang, D. D. Tang, 1992 .

Bipolar transistor design for optimized power-delay logic circuits

P. M. Solomon, D. D. Tang, P. Solomon, 1979 .

Design of mutually matching multiple-varactor array doubler for power

D. D. Tang, 1967 .

A circuit concept for reducing soft-error in high-speed memory cells

D. D. Tang, C. T. Chuang, 1987, 1987 Symposium on VLSI Circuits.

High-Speed Low-Power AC-coupled Complementary Push-pull

D. D. Tang, C. T. Chuang, 1991, 1991 Symposium on VLSI Circuits.

Contributors, Sep. 1975

R. J. Lomax, D. D. Tang, V. K. Tripathi, 1975 .

A 1.0-ns 5-kbit ECL RAM

G. P. Li, E. Hackbarth, D. D. Tang, 1986 .

A subnanosecond 5-kbit bipolar ECL RAM

Ching-Te Chuang, Tak H. Ning, D. D. Tang, 1988 .