S. Vangal

A six-port 57GB/s double-pumped nonblocking router core

A. Alvandpour, S. Vangal, N. Borkar, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

S. Vangal, G.E. Dermer, R. Nair, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS

S. Vangal, N. Borkar, S. Mathew, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

J. Tschanz, S. Narendra, V. De, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

S. Narendra, S. Borkar, S. Vangal, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications

A. Alvandpour, S. Vangal, N. Borkar, 2007, 2007 IEEE Symposium on VLSI Circuits.

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

J. Tschanz, S. Narendra, R. Krishnamurthy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Selective node engineering for chip-level soft error rate improvement [in CMOS]

S. Vangal, T. Karnik, P. Hazucha, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).