Vojin G. Oklobdzija

发表

Energy-Efficient Design Methodologies: High-Performance VLSI Adders

Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija, 2010, IEEE Journal of Solid-State Circuits.

A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2's complement multiplier for wireless baseband

Sanu Mathew, Bart R. Zeydel, Vojin G. Oklobdzija, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Design strategies for optimal multiplier circuits

R. Ravi, Charles U. Martel, Vojin G. Oklobdzija, 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

Energy efficient implementation of parallel CMOS multipliers with improved compressors

Dursun Baran, Vojin G. Oklobdzija, Mustafa Aktan, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Soft error filtered and hardened latch

Vojin G. Oklobdzija, Sayed Masoud Sayedi, Hossein Saidi, 2009, 2009 IEEE 8th International Conference on ASIC.

Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations

Vojin G. Oklobdzija, Nikola Nedovic, Christophe Giacomotto, 2006, PATMOS.

Conditional pre-charge techniques for power-efficient dual-edge clocking

Vojin G. Oklobdzija, Nikola Nedovic, Marko Aleksic, 2002, ISLPED '02.

Multiplier structures for low power applications in deep-CMOS

Dursun Baran, Vojin G. Oklobdzija, Mustafa Aktan, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

COMPUTER ORGANIZATION: Architecture

Vojin G. Oklobdzija, 1999 .

Simple and efficient CMOS circuit for fast VLSI adder realization

Vojin G. Oklobdzija, 1988, 1988., IEEE International Symposium on Circuits and Systems.

High-performance energy-efficient microprocessor design

Vojin G. Oklobdzija, Ram Krishnamurthy, 2006 .

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010

Naehyuck Chang, Naresh R. Shanbhag, Vojin G. Oklobdzija, 2010, ISLPED.

Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design

Bart R. Zeydel, Vojin G. Oklobdzija, Milena Vratonjic, 2006, PATMOS.

Optimal Circuits for Parallel Multipliers

R. Ravi, Charles U. Martel, Vojin G. Oklobdzija, 1998, IEEE Trans. Computers.

Timing and Energy Parameters

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

Low-Power Digital Signal Processing

Vojin G. Oklobdzija, 2001 .

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results

Vojin G. Oklobdzija, Dragan Maksimovic, Borivoje Nikolic, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Simulations of Interacting Many Body Systems Using P4

Vojin G. Oklobdzija, P. Lee, R. T. Scalettar, 1995, Int. J. High Speed Comput..

Synthesis of high-speed pass-transistor logic

Vojin G. Oklobdzija, B. Duchene, 1997 .

High-performance system design : circuits and logic

Vojin G. Oklobdzija, Ieee Circuits, 1999 .

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008

C. P. Ravikumar, Vojin G. Oklobdzija, Vijaykrishnan Narayanan, 2008, ISLPED.

Introduction

Vojin G. Oklobdzija, Belle Wei, 1991, J. VLSI Signal Process..

Low-energy logic circuit techniques for multiple valued logic

Vojin G. Oklobdzija, Dragan Maksimovic, K. Wayne Current, 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

Computer-Aided Analysis and Forecast of Integrated Circuit Yield

Vojin G. Oklobdzija, 2001 .

Energy-Delay Characteristics of CMOS Adders

Bart R. Zeydel, Vojin G. Oklobdzija, 2006 .

Some optimal schemes for ALU implementation in VLSI technology

Vojin G. Oklobdzija, Earl R. Barnes, 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

Design strategies for optimal hybrid final adders in a parallel multiplier

Vojin G. Oklobdzija, Paul F. Stelling, 1996, J. VLSI Signal Process..

Conditional techniques for low power consumption flip-flops

Vojin G. Oklobdzija, Nikola Nedovic, M. Aleksic, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

LowEnergy System Issues

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)

Vojin G. Oklobdzija, Ram Krishnamurthy, 2006 .

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming

Vojin G. Oklobdzija, Martine D. F. Schlag, Pak K. Chan, 1992, IEEE Trans. Computers.

Test Generation for FET Switching Circuits

Vojin G. Oklobdzija, J. Paul Roth, John F. Beetem, 1984, ITC.

Multiplexer based adder for media signal processing

Vojin G. Oklobdzija, A. A. Farooqui, F. Chechrazi, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Implementation-Level Impact on Low-Power Design

Vojin G. Oklobdzija, 2001 .

Clock-Powered CMOS for Energy-Efficient Computing

Vojin G. Oklobdzija, V. Oklobdzija, 2001 .

Design of a link-controller architecture for multiple serial link protocols

Vojin G. Oklobdzija, Poras T. Balsara, Lei Wang, 2010, 23rd IEEE International SOC Conference.

Low-Power Soft Error Hardened Latch

Vojin G. Oklobdzija, Hossein Karimiyan Alidash, 2010, J. Low Power Electron..

Design of power efficient VLSI arithmetic: speed and power trade-offs

Ram Krishnamurthy, Vojin G. Oklobdzija, 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

Clocked CMOS Adiabatic Logic with Single AC Power Supply

Vojin G. Oklobdzija, Dragan Maksimovic, D. Maksimović, 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

Logic Style Comparison for Ultra Low Power Operation in 65nm Technology

Bart R. Zeydel, Vojin G. Oklobdzija, Mandeep Singh, 2007, PATMOS.

An ASIC macro cell multiplier for complex numbers

Vojin G. Oklobdzija, D. Villeger, T. Soulas, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

Clocked Storage Elements in Digital Systems

Vojin G. Oklobdzija, Nikola Nedovic, 2006 .

A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach

Vojin G. Oklobdzija, David Villeger, Simon S. Liu, 1996, IEEE Trans. Computers.

Clocked storage elements robust to process variations

Vojin G. Oklobdzija, Mustafa Aktan, Joosik Moon, 2009, 2009 IEEE 8th International Conference on ASIC.

Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations

Bart R. Zeydel, Vojin G. Oklobdzija, 2006, PATMOS.

Energy-delay estimation technique for high-performance microprocessor VLSI adders

Sanu Mathew, Ram Krishnamurthy, Bart R. Zeydel, 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

An integrated multiplier for complex numbers

Vojin G. Oklobdzija, Thierry Soulas, David Villeger, 1994, J. VLSI Signal Process..

Comparative analysis of double-edge versus single-edge triggered clocked storage elements

Vojin G. Oklobdzija, Nikola Nedovic, Marko Aleksic, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A low power symmetrically pulsed dual edge–triggered flip–flop

William W. Walker, Vojin G. Oklobdzija, Nikola Nedovic, 2002 .

Architectural considerations for energy efficiency

Bart R. Zeydel, Vojin G. Oklobdzija, Hoang Q. Dao, 2005, 2005 International Conference on Computer Design.

Differential and pass-transistor CMOS logic for high-performance systems

Vojin G. Oklobdzija, 1997, 1997 21st International Conference on Microelectronics. Proceedings.

Integrated power clock generators for low energy logic

Vojin G. Oklobdzija, Dragan Maksimovic, 1995, Proceedings of PESC '95 - Power Electronics Specialist Conference.

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers

Vojin G. Oklobdzija, Nikola Nedovic, K. Wayne Current, 2005, PATMOS.

Pass-transistor adiabatic logic using single power-clock supply

Vojin G. Oklobdzija, Dragan Maksimovic, Fengcheng Lin, 1997 .

A Read Channel for Magnetic Recording

Vojin G. Oklobdzija, V. Oklobdzija, 2001 .

Design Flow and CAD tools for asynchronous design of sequential library cells

Vojin G. Oklobdzija, Christian Piguet, Cédric Cuche, 2002 .

Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology

Vojin G. Oklobdzija, D. Villeger, 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.

A unified approach in the analysis of latches and flip-flops for low-power systems

Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Improved CLA scheme with optimized delay

Vojin G. Oklobdzija, Brian D. Lee, 1991, J. VLSI Signal Process..

The Computer Engineering Handbook - 2 Volume Set

Vojin G. Oklobdzija, 2019 .

Low-Power Soft Error Hardened Latch

Vojin G. Oklobdzija, Hossein Karimiyan Alidash, 2009, PATMOS.

The Computer Engineering Handbook: Electrical Engineering Handbook

Vojin G. Oklobdzija, Richard C. Dorf, 2001 .

Comparison of high-performance VLSI adders in the energy-delay space

Sanu Mathew, Ram Krishnamurthy, Bart R. Zeydel, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Digital System Clocking: High-Performance and Low-Power Aspects

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

StateoftheArt Clocked Storage Elements in CMOS Technology

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

On Implementing Addition in VLSI Technology

Vojin G. Oklobdzija, Earl R. Barnes, 1988, J. Parallel Distributed Comput..

Dual-edge triggered storage elements and clocking strategy for low-power systems

Vojin G. Oklobdzija, Nikola Nedovic, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploration of switching activity behavior of addition algorithms

Dursun Baran, Vojin G. Oklobdzija, Mustafa Aktan, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Clocking and clocked storage elements in a multi-gigahertz environment

Vojin G. Oklobdzija, 2003, IBM J. Res. Dev..

Digital design and fabrication

Vojin G. Oklobdzija, 2017 .

The Computer Engineering Handbook

Vojin G. Oklobdzija, 2007 .

Reduced Instruction Set Computing

Vojin G. Oklobdzija, V. Oklobdzija, 1999, Wiley Encyclopedia of Computer Science and Engineering.

Performance Comparison of VLSI Adders Using Logical Effort

Vojin G. Oklobdzija, Hoang Q. Dao, 2002, PATMOS.

Algorithmic design of a hierarchical and modulator leading zero detector circuit

Vojin G. Oklobdzija, 1993 .

General method in synthesis of pass-transistor circuits

Vojin G. Oklobdzija, Borivoje Nikolic, Dejan Markovic, 2000 .

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

Vojin G. Oklobdzija, Nikola Nedovic, K. Wayne Current, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Computer arithmetic for the processing of media signals

Vojin G. Oklobdzija, Aamir A. Farooqui, 2000, SPIE Optics + Photonics.

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Vladimir Stojanovic, Vojin G. Oklobdzija, V. Oklobdzija, 1999, IEEE J. Solid State Circuits.

Reduced Instruction Set Computing

Vojin G. Oklobdzija, 1999 .

Early branch prediction circuit for high performance digital signal processors

Vojin G. Oklobdzija, A. A. Farooqui, 1998, Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186).

Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters

Vojin G. Oklobdzija, Michael A. Soderstrand, Richard H. Strandberg, 1996, J. VLSI Signal Process..

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

Vojin G. Oklobdzija, Matthew M. Ziegler, Thomas Mitchell, 2009, PATMOS.

Low- and ultra low-power arithmetic units: design and comparison

Bart R. Zeydel, Vojin G. Oklobdzija, Milena Vratonjic, 2005, 2005 International Conference on Computer Design.

Delay optimization of carry-skip adders and block carry-lookahead adders

Vojin G. Oklobdzija, Martine D. F. Schlag, Pak K. Chan, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

An implementation algorithm and design of a novel leading zero detector circuit

Vojin G. Oklobdzija, V. Oklobdzija, 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.

High-Performance Computer Arithmetic and Implementations: Introduction

Vojin G. Oklobdzija, 1994, HICSS.

HighPerformance Arithmetic Units

Vojin G. Oklobdzija, 1999 .

Differential and pass-transistor CMOS logic for high performance systems

Vojin G. Oklobdzija, 1998 .

Timing characterization of dual-edge triggered flip-flops

Vojin G. Oklobdzija, Nikola Nedovic, Marko Aleksic, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Energy optimization of pipelined digital systems using circuit sizing and supply scaling

Bart R. Zeydel, Vojin G. Oklobdzija, Hoang Q. Dao, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparative analysis of latches and flip-flops for high-performance systems

Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Guest editors' introduction

Vojin G. Oklobdzija, Belle Wei, 1996, J. VLSI Signal Process..

Computing at the ultimate low-energy limits

Vojin G. Oklobdzija, 2010, SBCCI '10.

Timing and Clocking

Vojin G. Oklobdzija, 2001 .

Proceedings of the 2014 international symposium on Low power electronics and design

C. P. Ravikumar, Vojin G. Oklobdzija, Vijaykrishnan Narayanan, 2006 .

An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

Vojin G. Oklobdzija, V. Oklobdzija, 1994, IEEE Trans. Very Large Scale Integr. Syst..

ISLPED'08 : proceedings of the 2008 International Symposium on Low Power Electronics and Design, Bangalore, India, August 11 - 13, 2008

Vojin G. Oklobdzija, Vijaykrishnan Narayanan, Ali Keshavarzi, 2008 .

Switching activity calculation of VLSI adders

Dursun Baran, Vojin G. Oklobdzija, Mustafa Aktan, 2009, 2009 IEEE 8th International Conference on ASIC.

High-Performance System Design

Vojin G. Oklobdzija, V. Oklobdzija, 1999 .

Efficient mapping of addition recurrence algorithms in CMOS

Bart R. Zeydel, Vojin G. Oklobdzija, Ties Kluter, 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

HighPerformance System Issues

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

Clocking and Clocked Storage Elements in Multi-GHz Environment

Vojin G. Oklobdzija, 2002, PATMOS.

Area-time optimal adder with relative placement generator

Vojin G. Oklobdzija, Sadiq M. Sait, Aamir A. Farooqui, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Energy Optimization of High-Performance Circuits

Bart R. Zeydel, Vojin G. Oklobdzija, Hoang Q. Dao, 2003, PATMOS.

An On-Line Square Root Algorithm

Milos D. Ercegovac, Vojin G. Oklobdzija, V. Oklobdzija, 1982, IEEE Transactions on Computers.

An efficient transistor optimizer for custom circuits

William W. Walker, Vojin G. Oklobdzija, Xiao Yan Yu, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Theory of Clocked Storage Elements

Vladimir Stojanovic, Vojin G. Oklobdzija, Dejan Markovic, 2003 .

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation

Kevin J. Nowka, Vojin G. Oklobdzija, Hoang Q. Dao, 2001, ISLPED '01.

Design of Energy Efficient Digital Circuits

Bart R. Zeydel, Vojin G. Oklobdzija, V. Oklobdzija, 2006 .

Architectures for Low Power

Vojin G. Oklobdzija, 2001 .

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

Vojin G. Oklobdzija, Dragan Maksimovic, Borivoje Nikolic, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Implementing multiply-accumulate operation in multiplication time

Vojin G. Oklobdzija, Paul F. Stelling, 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders

Dursun Baran, Vojin G. Oklobdzija, Mustafa Aktan, 2015, 2015 IEEE 22nd Symposium on Computer Arithmetic.

Design and optimization of sense–amplifier–based flip–flops

Vojin G. Oklobdzija, Borivoje Nikolic, 1999 .

Dynamic flip-flop with improved power

Vojin G. Oklobdzija, Nikola Nedovic, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Design Methodology for Clocked Storage Elements Robust to Process Variations

Vojin G. Oklobdzija, Mustafa Aktan, Joosik Moon, 2009, 2009 Second International Conference on Advances in Circuits, Electronics and Micro-electronics.

Low-Power Design of Systems on Chip

Vojin G. Oklobdzija, 2001 .

Future directions in clocking multi-ghz systems

Vojin G. Oklobdzija, Jens Sparsø, 2002, ISLPED '02.

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

Vojin G. Oklobdzija, David Villeger, 1995, IEEE Trans. Very Large Scale Integr. Syst..

Digital Filter Design

Vojin G. Oklobdzija, 2001 .

VLSI implementation of early branch prediction circuits for high performance computing

Vojin G. Oklobdzija, Aamir A. Farooqui, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

Vojin G. Oklobdzija, Mandeep Singh, Christophe Giacomotto, 2008, PATMOS.