K. Lokesh Krishna

Implementation of a CMOS Operational Amplifier using Composite Cascode Stages

K. Sai Kumar, K. Lokesh Krishna, P. R. Sidda Reddy, 2019 .

A 1V second order delta sigma ADC in 130nm CMOS

K. Lokesh Krishna, D. Reena, T. Ramashri, 2014, International Conference on Information Communication and Embedded Systems (ICICES2014).

Design and VLSI Implementation of Second Order Sigma-Delta Modulation ADC for I-UWB Receiver

K. Lokesh Krishna, D. Srihari, T. Ramashri, 2013 .

VLSI DESIGN OF 12-BIT ADC WITH 1GSPS IN 180NM CMOS INTEGRATING WITH SAR AND TWO-STEP FLASH ADC

K. Lokesh Krishna, T. Ramashri, 2014 .

An 8-Bit Charge Redistribution SAR ADC

K. Lokesh Krishna, A. Krishna Mohan, Yahya Mohammed Ali Al-Naamani, 2020 .

Verilog Implementation of UART with Status Register

K. Lokesh Krishna, B. Silpa, K. Anuradha, 2014 .

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

K. Lokesh Krishna, Yahya Mohammed Ali Al-Naamani, A. M. Guna Sekhar, 2020 .

A 6-Bit Low Power SAR ADC

K. Lokesh Krishna, K. Anuradha, Alfakhri M. Murshed, 2018 .

A High Speed Two Step Flash ADC

K. Lokesh Krishna, Yahya Mohammed Ali Al-Naamani, K. Anuradha, 2018 .