Pin Su

发表

Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM

Ching-Te Chuang, Ming-Long Fan, Pin Su, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A body-contact SOI MOSFET model for circuit simulation

Pin Su, Chenming Hu, S.K.H. Fung, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Design and analysis of ultra-thin-body SOI based subthreshold SRAM

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2009, ISLPED.

Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD

Pin Su, Weidong Liu, Chenming Hu, 2002, Proceedings International Symposium on Quality Electronic Design.

An Impact Ionization Model for SO1 Circuit Simulation

Ali M. Niknejad, Pin Su, Mansun Chan, 2002 .

Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices

Ching-Te Chuang, Vita Pi-Ho Hu, Pin Su, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, Proceedings of 2013 International Conference on IC Design & Technology (ICICDT).

Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, 2012 IEEE International Conference on IC Design & Technology.

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

Ming-Long Fan, Pin Su, Ko-Chun Lee, 2015, Microelectron. Reliab..

Analysis of power-performance for Ultra-Thin-Body GeOI logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Temperature stress testing of laser modules for the uncontrolled environment

Pin Su, 1991, Other Conferences.

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Challenges and Designs of TFET for Digital Applications

Ching-Te Chuang, Ming-Long Fan, Pin Su, 2016 .

A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015 .

Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs

Ching-Te Chuang, Vita Pi-Ho Hu, Pin Su, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Present Status and Future Direction of BSIM SOI Model for High- Performance/Low-Power/RF Application

Pin Su, Chenming Hu, S Fung, 2001 .

A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation

Ali M. Niknejad, Pin Su, Mansun Chan, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Study on Isolation and Purification of Antifungal Active Compoents of Bacillus Cereus A168

Pin Su, Ya Zhang, Xiao Lan Liao, 2013 .

Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, International Symposium on Quality Electronic Design (ISQED).

Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Ching-Te Chuang, Vita Pi-Ho Hu, Pin Su, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations

Ching-Te Chuang, Pin Su, Po-Tsang Huang, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells

Ching-Te Chuang, Pin Su, Chang-Hung Yu, 2016, ISLPED.

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, Microelectron. Reliab..

Independently-controlled-Gate FinFET Schmitt Trigger sub-threshold SRAMs

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2010 .

Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling

Ching-Te Chuang, Pin Su, Yin-Nien Chen, 2016, 2016 International Conference on IC Design and Technology (ICICDT).