Fu-Chien Chiu

发表

Inserted substrate pickup style with external resistance in an ESD NMOS transistor

Chih-Yao Huang, Fu-Chien Chiu, Bo-Chen Lin, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

A SCR-buried BJT device for robust ESD protection with high latchup immunity in high-voltage technology

Jen-Chou Tseng, Chih-Yao Huang, Fu-Chien Chiu, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Design optimization of ESD protection and latchup prevention for a serial I/O IC

Ming-Dou Ker, Jeng-Chou Tseng, Wei-Fang Chen, 2004, Microelectron. Reliab..

An investigation of surface state capture cross-sections for metal-oxide-semiconductor field-effect transistors using HfO2 gate dielectrics

Fu-Chien Chiu, Huey-Liang Hwang, Wen-Chieh Shih, 2007, Microelectron. Reliab..

A high latchup - Immune ESD protection SCR-incorporated BJT in deep submicron technology

Jen-Chou Tseng, Chih-Yao Huang, Fu-Chien Chiu, 2013, Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Electrical properties of metal-HfO2-silicon system measured from metal-insulator-semiconductor capacitors and metal-insulator-semiconductor field-effect transistors using HfO2 gate dielectric

Fu-Chien Chiu, Joseph Ya-min Lee, Shun-An Lin, 2005, Microelectron. Reliab..

Electrical characterization and carrier transportation in Hf-silicate dielectrics using ALD gate stacks for 90 nm node MOSFETs

Fu-Chien Chiu, H. W. Chen, Chuan-Hsi Liu, 2008 .

Electron conduction mechanism and band diagram of sputter-deposited Al∕ZrO2∕Si structure

Che-Wei Chang, Chih-Yao Huang, Fu-Chien Chiu, 2005 .

Current conduction mechanisms in Pr2O3/oxynitride laminated gate dielectrics

Fu-Chien Chiu, Tung-Ming Pan, T. Pan, 2009 .

Reliability properties of metal-oxide-semiconductor capacitors using HfO2 high-κ dielectric

Fu-Chien Chiu, Chun-Heng Chen, Tai-Bor Wu, 2007 .

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Ming-Dou Ker, Jen-Chou Tseng, Chih-Yao Huang, 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

Electrical conduction mechanisms of metal∕La2O3∕Si structure

Fu-Chien Chiu, J. Lee, F. Chiu, 2005 .

Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

Fu-Chien Chiu, 2013 .

Interface characterization and carrier transportation in metal/HfO2/silicon structure

Fu-Chien Chiu, F. Chiu, 2006 .

Optical and electrical characterizations of cerium oxide thin films

Fu-Chien Chiu, Chih-Ming Lai, C. Lai, 2010 .

Conduction mechanism of resistive switching films in MgO memory devices

Fu-Chien Chiu, Wen-Chieh Shih, F. Chiu, 2012 .

An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

Jen-Chou Tseng, Chih-Yao Huang, Fu-Chien Chiu, 2012, IEEE Transactions on Device and Materials Reliability.