Nabil Badereddine

发表

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.

Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solution

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2005 .

Failure Analysis and Test Solutions for Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Impact of Resistive-Bridging Defects in SRAM Core-Cell

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

Power-Aware Scan Testing for Peak Power Reduction

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2005 .

On using address scrambling to implement defect tolerance in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 IEEE International Test Conference.

Test solution for data retention faults in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, J. Electron. Test..

Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan Testing

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2006 .

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 IEEE International Test Conference (ITC).

Low-power SRAMs power mode control logic: Failure analysis and test solutions

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE International Test Conference.

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 22nd Asian Test Symposium.

Defect analysis in power mode control logic of low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 17th IEEE European Test Symposium (ETS).

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, J. Electron. Test..

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Setting test conditions for improving SRAM reliability

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability

Elena I. Vatajelu, Arnaud Virazel, Alberto Bosio, 2013, 2013 18th IEEE European Test Symposium (ETS).

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

Detecting NBTI induced failures in SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 28th VLSI Test Symposium (VTS).

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 15th IEEE European Test Symposium.