T. Koide

发表

Fully parallel single and two-stage associative memories for high speed pattern matching

H.J. Mattausch, M.A. Abedin, T. Koide, 2008, 2008 International Conference on Electrical and Computer Engineering.

Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory

H.J. Mattausch, A. Ahmadi, T. Koide, 2007, 2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing.

Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance

H.J. Mattausch, T. Gyoten, S. Fukae, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair

T. Koide, S. Wakabayashi, S. Nakaya, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

An LSI hardware design for online character recognition using associative memory

H.J. Mattausch, A. Ahmadi, T. Koide, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Reference-pattern learning and optimization from an input-pattern stream for associative-memory-based pattern-recognition systems

H.J. Mattausch, T. Koide, Y. Shirakawa, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Optimized multi-stage minimum-distance-search circuit with feedback-stabilization for fully-parallel associative memories

H.J. Mattausch, T. Koide, K. Kamimura, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Associative-memory-based prototype LSI with recognition and on-line learning capability and its application to handwritten characters

H.J. Mattausch, T. Koide, W. Imafuku, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Low power bank-based multi-port SRAM design due to bank standby mode

H.J. Mattausch, T. Koide, T. Hironaka, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

VLSI-architecture for enabling multiple parallel associative searches with standard SRAM macros

T. Kumaki, H.J. Mattausch, T. Koide, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Multi-port CAM based VLSI architecture for Huffman coding with real-time optimized code word table

T. Kumaki, H. Noda, Y. Kuroda, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

A circuit partitioning algorithm under path delay constraints

T. Koide, S. Wakabayashi, J. Minami, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Multi-Bank Register File for Increased Performance of Highly-Parallel Processors

H.J. Mattausch, Koh Johguchi, T. Koide, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

H.J. Mattausch, H. Adachi, Y. Harada, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A low-power video segmentation LSI with boundary-active-only architecture

H.J. Mattausch, T. Koide, O. Kiriyama, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Analog-circuit-component optimization with genetic algorithm

H.J. Mattausch, T. Koide, K. Takemura, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

A hierarchical placement method for standard cell layout based on wire length driven clustering

T. Koide, S. Wakabayashi, H. Kubota, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors

H.J. Mattausch, T. Koide, K. Johguchi, 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

Huffman Encoding Architecture with Self-Optimizing Performance and Multiple CAM-Match Utilization

T. Kumaki, M. Ishizaki, H.J. Mattausch, 2006, TENCON 2006 - 2006 IEEE Region 10 Conference.

A novel hierarchical multi-port cache

H.J. Mattausch, T. Koide, T. Hironaka, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).