Shoto Tamai

发表

Analysis of bit cost for stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Study of stacked NOR type MRAM for universal memory

Shigeyoshi Watanabe, Shoto Tamai, 2009 .

Process step and analysis of bit cost for stacked type MRAM with NOR structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2015 .

Design method of stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Novel cell array noise cancelling design scheme for stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Proposal of Stacked Type Memory/Logic Circuit Array and Its Application to LUT (Look Up Table)

Shigeyoshi Watanabe, Shoto Tamai, Takumi Sato, 2016 .

Low cost stacked type NOR MRAM with 1 MOSFET/1 MTJ cell structure and shared source line (SL) scheme

Shigeyoshi Watanabe, Shoto Tamai, 2015 .

Design Method of Stacked Type NAND MRAM with Ultra Low Bit Cost

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Assisted MRAM with NAND Structured Cell

Shoto Tamai, Shigeyoshi Watanabe, 2013 .

Design method of stacked type thermally assisted MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Design Scheme Considering Memory Cell Array Noise for Stacked Type MRAM with NAND Structured Cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .