Xijiang Lin

发表

Power Aware Embedded Test

Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, 2011, 2011 Asian Test Symposium.

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

Chen Wang, Kun-Han Tsai, Xijiang Lin, 2006, 2006 15th Asian Test Symposium.

Detecting and diagnosing open defects

Dat Tran, Bruce Swanson, Xijiang Lin, 2010, 2010 IEEE International Test Conference.

Test compaction for small-delay defects using an effective path selection scheme

Jianbo Li, Krishnendu Chakrabarty, Dong Xiang, 2013, TODE.

Measures to improve delay fault testing on low-cost testers - a case study

Matthias Beck, Xijiang Lin, Olivier Barondeau, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Programmable Logic BIST for At-speed Test

Xijiang Lin, Yu Huang, 2007, 16th Asian Test Symposium (ATS 2007).

On gate function based tests for scan designs

Sudhakar M. Reddy, Xijiang Lin, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Test Power Reduction by Blocking Scan Cell Outputs

Janusz Rajski, Xijiang Lin, 2008, 2008 17th Asian Test Symposium.

High-frequency, at-speed scan testing

Janusz Rajski, Nagesh Tamarapalli, Bruce Swanson, 2003, IEEE Design & Test of Computers.

Preferred Fill: A Scalable MethodtoReduceCapture PowerforScan BasedDesigns

Irith Pomeranz, Xijiang Lin, S. Remersaro, 2006 .

On Utilizing Test Cube Properties to Reduce Test Data Volume Further

Janusz Rajski, Xijiang Lin, 2012, 2012 IEEE 21st Asian Test Symposium.

Techniques for improving the efficiency of sequential circuit test generation

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Multicycle-aware At-speed Test Methodology

Kun-Han Tsai, Xijiang Lin, 2013, 2013 22nd Asian Test Symposium.

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains

Xijiang Lin, Mark Kassab, Tom Waayers, 2010, 2010 IEEE International Test Conference.

Low capture power at-speed test in EDT environment

Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, 2010, 2010 IEEE International Test Conference.

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Xijiang Lin, 2011 .

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

Xiaoqing Wen, Dong Xiang, Bhargab B. Bhattacharya, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits

Sudhakar M. Reddy, Janusz Rajski, Xijiang Lin, 2015, 2015 28th International Conference on VLSI Design.

SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration

Irith Pomeranz, Sudhakar M. Reddy, Wu-Tung Cheng, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Low Shift and Capture Power Scan Tests

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

TEA: A Test Generation Algorithm for Designs with Timing Exceptions

Irith Pomeranz, Wu-Tung Cheng, Xijiang Lin, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

Scan tests with multiple fault activation cycles for delay faults

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 24th IEEE VLSI Test Symposium.

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults

Irith Pomeranz, Xijiang Lin, I. Pomeranz, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test Generation for Timing-Critical Transition Faults

Xijiang Lin, M. Kassab, J. Rajski, 2007, 16th Asian Test Symposium (ATS 2007).

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection

Sudhakar M. Reddy, Wu-Tung Cheng, Xijiang Lin, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Test Generation for Interconnect Opens

Janusz Rajski, Xijiang Lin, 2008, 2008 IEEE International Test Conference.

Test Challenges of Intel IA Cores

Xijiang Lin, Kun-Han Tsai, Uri Shpiro, 2020, 2020 IEEE International Test Conference (ITC).

MIX : A Test Generation System for

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1997 .

Logic design for on-chip test clock generation - implementation details and impact on delay test quality

Matthias Beck, Xijiang Lin, Olivier Barondeau, 2005, Design, Automation and Test in Europe.

Low-Power Scan Operation in Test Compression Environment

Janusz Rajski, Jerzy Tyszer, Xijiang Lin, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New procedures for identifying undetectable and redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Transistor stuck-on fault detection tests for digital CMOS circuits

Sudhakar M. Reddy, Janusz Rajski, Xijiang Lin, 2016, 2016 21th IEEE European Test Symposium (ETS).

Low power testing - What can commercial DFT tools provide?

Xijiang Lin, 2011, 2011 International Green Computing Conference and Workshops.

On generating high quality tests based on cell functions

Sudhakar M. Reddy, Xijiang Lin, 2015, 2015 IEEE International Test Conference (ITC).

MIX: a test generation system for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings Eleventh International Conference on VLSI Design.

Functional Broadside Test Generation Using a Commercial ATPG Tool

Irith Pomeranz, Bo Yao, Xijiang Lin, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Low Power Scan Shift and Capture in the EDT Environment

Janusz Rajski, Jerzy Tyszer, Xijiang Lin, 2008, 2008 IEEE International Test Conference.

Experimental results of forward-looking reverse order fault simulation on industrial circuits with scan

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 2001, Proceedings 10th Asian Test Symposium.

On removing redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Timing-Aware ATPG

Benoit Nadeau-Dostie, Xijiang Lin, Mark Kassab, 2014, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits.

Propagation delay fault: a new fault model to test delay faults

Xijiang Lin, J. Rajski, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Propagation delay fault: a new fault model to test delay faults

Janusz Rajski, Xijiang Lin, 2005, ASP-DAC.

The impacts of untestable defects on transition fault testing

Janusz Rajski, Xijiang Lin, 2006, 24th IEEE VLSI Test Symposium.

On applying scan based structural test for designs with dual-edge triggered flip-flops

Xijiang Lin, 2017, 2017 IEEE International Test Conference (ITC).

Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture

Nandu Tendolkar, Greg Aldrich, Bruce Swanson, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults

Janusz Rajski, Wu-Tung Cheng, Xijiang Lin, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999 .

Scan-Based Tests with Low Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, IEEE Design & Test of Computers.

Adaptive Low Shift Power Test Pattern Generator for Logic BIST

Janusz Rajski, Xijiang Lin, 2010, 2010 19th IEEE Asian Test Symposium.

On Reducing Scan Shift Activity at RTL

Wu-Tung Cheng, Yu Huang, Jennifer Dworak, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reducing Scan Shift Power at RTL

Wu-Tung Cheng, Jennifer Dworak, Xijiang Lin, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, ICCAD 2002.

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 2006 IEEE International Test Conference.

Full scan fault coverage with partial scan

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Using dynamic shift to reduce test data volume in high-compression designs

Janusz Rajski, Xijiang Lin, Mark Kassab, 2014, 2014 19th IEEE European Test Symposium (ETS).

Test Generation for Designs with On-Chip Clock Generators

Xijiang Lin, Mark Kassab, 2009, 2009 Asian Test Symposium.

TestGeneration forInterconnect Opens

Janusz Rajski, Xijiang Lin, 2008 .

On static test compaction and test pattern ordering for scan designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Test generation for designs with multiple clocks

Xijiang Lin, Rob Thompson, 2003, DAC '03.

Power Supply Droop and Its Impacts on Structural At-Speed Testing

Xijiang Lin, 2012, 2012 IEEE 21st Asian Test Symposium.

On finding undetectable and redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells

Xijiang Lin, Yu Huang, 2008, J. Electron. Test..

On Generating Fault Diagnosis Patterns for Designs with X Sources

Sudhakar M. Reddy, Xijiang Lin, 2019, 2019 IEEE European Test Symposium (ETS).

On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation

Andreas Glowatz, Xijiang Lin, Wu-Tung Cheng, 2021, 2021 IEEE 30th Asian Test Symposium (ATS).

Timing Critical Path Validation for Intel ATOM Cores Using Structural Test

Kun-Han Tsai, Xijiang Lin, Khen Wee, 2021, 2021 IEEE 39th VLSI Test Symposium (VTS).