Sang-Hyeok Chu

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jiho Joo, 2015, IEEE Journal of Solid-State Circuits.

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

Deog-Kyoon Jeong, Taeho Kim, Sang-Hyeok Chu, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Deog-Kyoon Jeong, Han-Gon Ko, Sung-Yong Cho, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jiho Joo, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Deog-Kyoon Jeong, Gyu-Seob Jeong, Sang-Hyeok Chu, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

Deog-Kyoon Jeong, Gyu-Seob Jeong, Sang-Hyeok Chu, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS

Taeik Kim, Gyu-Seob Jeong, Jeongho Hwang, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

Sang-Hyeok Chu, Seung-Yeob Baek, Taehun Yoon, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- ${\rm G}_{\rm m}$ Bias

Deog-Kyoon Jeong, Gyu-Seob Jeong, Haram Ju, 2016, IEEE Journal of Solid-State Circuits.