Avaneesh K. Dubey

发表

Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect

Avaneesh K. Dubey, R. K. Nagaria, 2019, J. Circuits Syst. Comput..

Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure

Rahul Jain, Avaneesh K. Dubey, Rajendra K. Nagaria, 2017, 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON).

Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique

R. K. Nagaria, Avaneesh K. Dubey, 2018, J. Circuits Syst. Comput..

Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit

Ankur Kumar, Avaneesh K. Dubey, Rajendra Kumar Nagaria, 2021 .

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

R. K. Nagaria, Avaneesh K. Dubey, R. Nagaria, 2018, Microelectron. J..

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

Avaneesh K. Dubey, R. K. Nagaria, R. Nagaria, 2019, Analog Integrated Circuits and Signal Processing.

An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic

Avaneesh K. Dubey, Vikrant Varshney, Kamal Prakash Pandey, 2020, 2020 IEEE Students Conference on Engineering & Systems (SCES).

Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process

R.K. Nagaria, Ankur Kumar, Avaneesh K. Dubey, 2018, 2018 3rd International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH).

Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications

Avaneesh K. Dubey, R. K. Nagaria, Vikrant Varshney, 2021 .

A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications

Avaneesh K. Dubey, R. Nagaria, Vikrant Varshney, 2019, 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON).

Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs

Avaneesh K. Dubey, R. Nagaria, P. K. Pal, 2020 .

Enhanced slew rate, constant-gm rail-to-rail OpAmp using 1:2 current mirror biasing technique

Avaneesh K. Dubey, R. K. Nagaria, Pratosh K. Pal, 2016, 2016 International Conference on Computing, Communication and Automation (ICCCA).

A 0.18 µm β-Ga2O3 MOSFET Using Al2O3/HfO2/SiO2 Gate Dielectric for Low-VTH High-Power Electronics Applications

Avaneesh K. Dubey, R. Nagaria, R. Chauhan, 2021, Lecture Notes in Electrical Engineering.

Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness

Avaneesh K. Dubey, R. Nagaria, P. K. Pal, 2019, 2019 IEEE Conference on Information and Communication Technology.

Voltage comparison based high speed & low power domino circuit for wide fan-in gates

Sankit R. Kassa, Avaneesh K. Dubey, Rajendra Kumar Nagaria, 2016, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).