Jiann-Chyi Rau

发表

Low-capture-power X-filling method based on architecture using selection expansion

Yu-Ting Chung, Jiann-Chyi Rau, 2018, 2018 IEEE International Conference on Applied System Invention (ICASI).

An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits

Jiann-Chyi Rau, Kuo-Chun Kuo, J. Rau, 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

Reducing switching activity by test slice difference technique for test volume compression

Po-Han Wu, Jiann-Chyi Rau, Wei-Lin Li, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Multi-cycle compress technique for high-speed IP in low-cost environment

Po-Han Wu, Jiann-Chyi Rau, Gong-Han Chen, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A compact factored form for a Boolean function

Shih-Chieh Chang, Jiann-Chyi Rau, Y. M. Chen, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

The AB-filling methodology for power-aware at-speed scan testing

Jiann-Chyi Rau, Kung-Han Chen, Tsung-Tang Chen, 2010, 2010 IEEE International Test Conference.

Test Slice Difference Technique for Low-Transition Test Data Compression

Po-Han Wu, Jiann-Chyi Rau, Wei-Lin Li, 2012 .

An efficient mechanism for debugging RTL description

Yi-Yuan Chang, Chia-Hung Lin, Jiann-Chyi Rau, 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information

Jiann-Chyi Rau, Ching-hsiu Lin, Jun-Yi Chang, 2004 .

The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design

Jiann-Chyi Rau, Yi-Chen Lin, Chia-Jung Liu, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

The efficient TAM design for core-based SOCs testing

Po-Han Wu, Jiann-Chyi Rau, Chih-Lung Chien, 2008 .

A novel reseeding mechanism for pseudo-random testing of VLSI circuits

Po-Han Wu, Jiann-Chyi Rau, Ying-Fu Ho, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs

Po-Han Wu, Jiann-Chyi Rau, Chih-Lung Chien, 2010 .

A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits

Wen-Ben Jone, Yu-Liang Wu, Shih-Chieh Chang, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment

Po-Han Wu, Jiann-Chyi Rau, 2011, IET Comput. Digit. Tech..

Multi-chains encoding scheme in low-cost ATE

Po-Han Wu, Jiann-Chyi Rau, Gong-Han Chen, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

Po-Han Wu, Jiann-Chyi Rau, Chien-Shiun Chen, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Test slice difference technique for low power encoding

Po-Han Wu, Jiann-Chyi Rau, Wei-Lin Li, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

A novel gated scan-cell scheme for low Capture Power (LCP) in at-speed testing

Jiann-Chyi Rau, Po-Han Wu, Ming-Ying Chiang, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

A broadcast-based test scheme for reducing test size and application time

Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A timing-driven pseudoexhaustive testing for VLSI circuits

Shih-Chieh Chang, Jiann-Chyi Rau, Shih-Chieh Chang, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient scheduling algorithm based on multi-frequency tam for SOC testing

Po-Han Wu, Jiann-Chyi Rau, Jia-Shing Ma, 2008 .

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

Po-Han Wu, Jiann-Chyi Rau, Chia-Jung Liu, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

ABroadcast-Based TestSchemeforReducing TestSize andApplication Time

Jiann-Chyi Rau, 2006 .

An efficient low-overhead policy for constructing multiple scan-chains

Jiann-Chyi Rau, Jun-Yi Chang, Ching-Hsiu Lin, 2004, 13th Asian Test Symposium.

Compact Test Pattern Selection for Small Delay Defect

Chien-Mo James Li, Jiann-Chyi Rau, Chia-Yuan Chang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A don't-care based image circuit for function verification

Shih-Chieh Chang, Jiann-Chyi Rau, Y. M. Chen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Optimal unknown bit filtering for test response masking

Jiann-Chyi Rau, Ding-ke Weng, Cheng-han Lin, 2012, 2012 International Symposium on Intelligent Signal Processing and Communications Systems.

Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

Krishnendu Chakrabarty, Jiann-Chyi Rau, Chun-Yi Kuo, 2012 .

Reconfigurable multiple scan-chains for reducing test application time of SOCs

Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits

Jiann-Chyi Rau, Po-Han Wu, Ying-Fu Ho, 2008 .

Low power multi-chains encoding scheme for SoC in low-cost environment

Po-Han Wu, Jiann-Chyi Rau, 2009, 2009 International Test Conference.

Power-aware compression scheme for multiple scan-chain

Po-Han Wu, Jiann-Chyi Rau, 2011 .

The star-routing algorithm based on Manhattan-Diagonal model for three layers channel routing

Po-Han Wu, Jiann-Chyi Rau, Yi-Chen Lin, 2009 .

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology

Po-Han Wu, Jiann-Chyi Rau, Wei-Lin Li, 2009, 2009 Asian Test Symposium.

An efficient test-data compaction for low power VLSI testing

Po-Han Wu, Jiann-Chyi Rau, Wei-Lin Li, 2008, 2008 IEEE International Conference on Electro/Information Technology.

A Scan-Based Lower-Power Testing Architecture for Modern Circuits

Jiann-Chyi Rau, Jia-Xiang Wang, 2021, 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction

Jiann-Chyi Rau, Po-Han Wu, Chung-Lin Wu, 2011 .