R. Malik

An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

S. Kudelka, N. Arnold, U. Gruening, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

High performance single work-function tungsten gate CMOS devices for gigabit DRAM

W. Bergner, Boyong He, C. Parks, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

M. Sherony, S. Narasimha, Y. Kohyama, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

W. Bergner, W. Mueller, J. Beintner, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond

W. Mueller, K. Varn, R. Jammy, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).