Jin Liu

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets

Ruiming Li, Dian Zhou, Jin Liu, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

Jin Liu, Xiaofeng Lin, Sooping Saw, 2005, IEEE Journal of Solid-State Circuits.

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets

Ruiming Li, Dian Zhou, Jin Liu, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.