Eric Delano

发表

Parallel execution core with different optimization characteristics to reduce the dynamic execution path

Donald Charles Soltis, Eric Delano, 2003 .

Verification of synchronism off-chip

Donald Charles Soltis, Eric Delano, Kevin David Safford, 2005 .

A CMOS RISC CPU designed for sustained high performance on large applications

Eric Delano, M. Forsyth, Jonathan P. Lotz, 1990 .

A 100 MHz superscalar PA-RISC CPU/coprocessor chip

Eric Delano, J. Yetter, W. Jaffe, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

WPM 3.7: A 90MHz CMOS RISC CPU Designed for Sustained Performance

Eric Delano, John R. Spencer, J. Yetter, 1990 .