H. Yamauchi

Embedded SRAM circuit design technologies for a 45nm and beyond

H. Yamauchi, 2007, 2007 7th International Conference on ASIC.

A discussion on SRAM circuit design trend in deeper nano-meter era

H. Yamauchi, 2008, 2008 International SoC Design Conference.

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

H. Yamauchi, Hsien-Yu Pan, Jui-Jen Wu, 2009, IEEE Journal of Solid-State Circuits.

Embedded SRAM trend in nano-scale CMOS

H. Yamauchi, 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses

H. Yamauchi, T. Suzuki, Y. Yamagami, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

H. Yamauchi, T. Suzuki, Y. Yamagami, 2008, IEEE Journal of Solid-State Circuits.

A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms

Meng-Fan Chang, Chih-Sheng Lin, Shyh-Shyuan Sheu, 2013, IEEE Journal of Solid-State Circuits.