C. Muzzy

Chip package interaction evaluation for a high performance 65nm and 45nm CMOS Technology in a stacked die package with C4 and wirebond interconnections

D. Danovitch, R. Hannon, E. Kinser, 2008, 2008 58th Electronic Components and Technology Conference.

Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology

J. Gill, C.-C. Yang, A. Carbone, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

J. Gill, D. Mocuta, D. Greenlaw, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL

J. Gill, C.-C. Yang, A. Carbone, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

D. Questad, J. Muncy, C. Carey, 2007, 2007 IEEE International Interconnect Technology Conferencee.

BEOL Integration of Highly Damage -Resistant Porous Ultra Low-K Material Using Direct CMP and Via-first Process

J. Gill, T. Spooner, S. Ponoth, 2006, 2006 International Interconnect Technology Conference.

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

C.-C. Yang, A. Cowley, D. Questad, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).