Hans Eveking

Hans Eveking, Martin Schweikert, Martin Braun, 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

Automatic Verification of Extensions of Hardware Descriptions

Hans Eveking, 1990, CAV.

Verwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen

Hans Eveking, Martin Schweikert, 2010, MBMV.

Automatic Verification of Extensions of Hardware Descriptions

Hans Eveking, H. Eveking, 1990, CAV.

Optimization and Resynthesis of Complex Data-Paths

Hans Eveking, Stefan Höreth, 1993, 30th ACM/IEEE Design Automation Conference.

(V)HDL-based verification of heterogeneous synchronous/asynchronous systems

Hans Eveking, H. Eveking, 1994, EURO-DAC '94.

Using sequence diagrams to specify and to generate RTL assertions

Hans Eveking, Tobias Dornes, Martin Schweikert, 2011 .

Formal synthesis for pipeline design

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 1999 .

Automatic verification of scheduling results in high-level synthesis

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 1999, DATE '99.

Formal verification: current use and future perspectives

Rolf Drechsler, Hans Eveking, J. A. Abraham, 2002, IEEE Design & Test of Computers.

On Consistency and Completeness of Property-Sets

Hans Eveking, Martin Braun, Martin Schickel, 2006, FDL.

A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set

Hans Eveking, Martin Schweikert, Martin Oberkönig, 2007, FDL.

Formal Verification of Designs with Complex Control by Symbolic Simulation

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 1999, CHARME.

Verifikation digitaler Systeme - eine Einführung in den Entwurf korrekter digitaler Systeme

Hans Eveking, 1991, Leitfäden und Monographien der Informatik.

Formal proofs from HDL descriptions

Laurence Pierre, Hans Eveking, Dominique Borrione, 1993 .

Formal verification of timing conditions

Hans Eveking, Christoph Mai, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Formale Verifikation von Systemeigenschaften unter Verwendung normalisierter formaler Spezifikationen

Hans Eveking, Tobias Dornes, 2010, MBMV.

VLSI-SOC: From Systems to Chips: IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), ... Federation for Information Processing)

Leandro Soares Indrusiak, Hans Eveking, Ricardo Reis, 2006 .

Formale Verifikation automatisch generierter Pipelinesysteme durch symbolische Simulation

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 1999 .

Improving testbench evaluation using normalized formal properties

Hans Eveking, Martin Oberkönig, Martin Schickel, 2009 .

Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften

Hans Eveking, Martin Oberkönig, Martin Schickel, 2009, MBMV.

Erzeugung von Operationseigenschaften aus UML Sequenzdiagrammen

Hans Eveking, Tobias Dornes, Martin Schweikert, 2011, MBMV.

On Consistency and Completeness of Property-Sets : Exploiting the Property-Based Design-Process

Hans Eveking, Martin Braun, Martin Schickel, 2006 .

Correct hardware design and verification methods : IFIP WG 10.5 Advanced Research Working Conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings

Hans Eveking, Paolo Camurati, 1995 .

Formale Verifikation eingebetteter Systeme

Hans Eveking, Claudia Blank, Malte Krieger, 2002 .

Correct Hardware Design and Verification Methods

Hans Eveking, Paolo Camurati, 1995, Lecture Notes in Computer Science.

Eine quantitative Vollständigkeitsanalyse für Eigenschaftssätze

Hans Eveking, Martin Oberkönig, Martin Schickel, 2008, MBMV.

False-path elimination and simplification of sequential acyclic descriptions with complex branching logic

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 2000 .

IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003

Leandro Soares Indrusiak, Hans Eveking, Manfred Glesner, 2003, VLSI-SoC.

Formale Verifikation der Register-Allokation

Hans Eveking, Gerd Ritter, Holger Hinrichsen, 2000, MBMV.

Analyse von Gegenbeispielen bei Verifikation mit unvollständigen Eigenschaftssätzen

Hans Eveking, Tobias Dornes, Martin Schweikert, 2011, MBMV.

MCML - a markup-language for a model-of-computation centred design and verification environment

Hans Eveking, Claudia Blank, Jens Levihn, 2002 .