David Z. Pan

发表

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

Jae-Seok Yang, Jiwoo Pak, Xin Zhao, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation

Chikaaki Kodama, Toshiya Kotani, Shigeki Nojima, 2016, ISPD.

Design for manufacturability and reliability for TSV-based 3D ICs

Jae-Seok Yang, Jiwoo Pak, Sung Kyu Lim, 2012, 17th Asia and South Pacific Design Automation Conference.

Flexible 2D layout decomposition framework for spacer-type double pattering lithography

David Z. Pan, Yongchan Ban, Kevin Lucas, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Design for manufacturing meets advanced process control: A survey

David Z. Pan, Peng Yu, Minsik Cho, 2008, Journal of Process Control.

Dealing with IC manufacturability in extreme scaling

Bei Yu, David Z. Pan, Jhih-Rong Gao, 2012, ICCAD '12.

An accurate sparse matrix based framework for statistical static timing analysis

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, ICCAD.

Keep it straight: teaching placement how to better handle designs with datapaths

Earl E. Swartzlander, David Z. Pan, Natarajan Viswanathan, 2012, ISPD '12.

Double patterning lithography friendly detailed routing with redundant via consideration

Kun Yuan, David Z. Pan, Katrina Lu, 2009, 2009 46th ACM/IEEE Design Automation Conference.

EBL Overlapping Aware Stencil Planning for MCC System

Shiyan Hu, Kun Yuan, David Z. Pan, 2016, ACM Trans. Design Autom. Electr. Syst..

DPlace2.0: A stable and efficient analytical placement based on diffusion

David Z. Pan, Tao Luo, 2008, 2008 Asia and South Pacific Design Automation Conference.

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

David Z. Pan, Ruchir Puri, Subhendu Roy, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Self-aligned double patterning compliant routing with in-design physical verification flow

David Z. Pan, Jhih-Rong Gao, Harshdeep Jawandha, 2013, Advanced Lithography.

Process Variation AwareOPCwithVariational Lithography Modeling

David Z. Pan, 2006 .

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization pdf

Azadeh Davoodi, Zhiru Zhang, Sergio Bampi, 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks

Meng Li, David Z. Pan, Qi-Xing Huang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Diffusion-based placement migration

David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization

David Z. Pan, Taehyun Kwon, Joon-Sung Yang, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs

David Z. Pan, Minsik Cho, Hongjoong Shin, 2006, Asia and South Pacific Conference on Design Automation, 2006..

OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions

Derong Liu, David Z. Pan, Subhendu Roy, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Wire width planning for interconnect performance optimization

Jason Cong, David Z. Pan, J. Cong, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing

David Z. Pan, Wuxi Li, Shounak Dhar, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout optimization algorithms for vlsi design and manufacturing

Gang Xu, David Z. Pan, Martin D. F. Wong, 2007 .

TSV stress aware timing analysis with applications to 3D-IC layout optimization

Jae-Seok Yang, Sung Kyu Lim, David Z. Pan, 2010, Design Automation Conference.

FPGA-Accelerated Spreading for Global Placement

David Z. Pan, Love Singhal, Shounak Dhar, 2019, 2019 IEEE High Performance Extreme Computing Conference (HPEC).

Incremental Layer Assignment for Timing Optimization

Derong Liu, David Z. Pan, Bei Yu, 2017, ACM Trans. Design Autom. Electr. Syst..

Electromigration-aware routing for 3D ICs with stress-aware EM modeling

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Lithography friendly routing: From construct-by-correction to correct-by-construction

David Z. Pan, D. Pan, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Simultaneous Placement and Clock Tree Construction for Modern FPGAs

David Z. Pan, Stephen Yang, Wuxi Li, 2019, FPGA.

Pyramids: An efficient computational geometry-based approach for timing-driven placement

David Z. Pan, Charles J. Alpert, Zhuo Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Optical proximity correction with hierarchical Bayes model

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2015, Advanced Lithography.

Integrated multi-operand electro-optic logic gates for optical computing

Richard A. Soref, Ray T. Chen, David Z. Pan, 2019, Applied Physics Letters.

Layout decomposition for quadruple patterning lithography and beyond

David Z. Pan, Bei Yu, D. Pan, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Fast incremental link insertion in clock networks for skew variability reduction

David Z. Pan, Anand Rajaram, D. Pan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Semi-supervised hotspot detection with self-paced multi-task learning

Ying Chen, Yayi Wei, David Z. Pan, 2019, ASP-DAC.

Implications of triple patterning for 14nm node design and patterning

Bei Yu, David Z. Pan, Kevin Lucas, 2012, Advanced Lithography.

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Novel and Unified Full-chip CMP Model Aware Dummy Fill Insertion Framework with SQP-Based Optimization Method

Xuan Zeng, David Z. Pan, Changhao Yan, 2020 .

Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock

Xi Chen, David Z. Pan, Peng Yu, 2008, 2008 IEEE International Conference on Bioinformatics and Biomedicine.

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, IEEE Transactions on Information Forensics and Security.

Methodology for standard cell compliance and detailed placement for triple patterning lithography

David Z. Pan, Jhih-Rong Gao, Xiaoqing Xu, 2013, ICCAD 2013.

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs

David Z. Pan, Yibo Lin, Wuxi Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs

Jae-Seok Yang, Sung Kyu Lim, David Z. Pan, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip

David Z. Pan, Wooyoung Jang, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Xuan Zeng, David Z. Pan, Hengliang Zhu, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters

Kun Yuan, David Z. Pan, Bei Yu, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits

Hao Chen, David Z. Pan, Xiyuan Tang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper)

Kun Yuan, Jae-Seok Yang, David Z. Pan, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interconnect sizing and spacing with consideration of couplingcapacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

VLSI CAD for emerging nanolithography

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Layout Decomposition for Triple Patterning Lithography

Kun Yuan, David Z. Pan, Duo Ding, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Self-aligned double patterning friendly configuration for standard cell library considering placement impact

David Z. Pan, Jhih-Rong Gao, Ru Huang, 2013, Advanced Lithography.

Directed self-assembly for advanced chips

David Z. Pan, D. Pan, 2018, Nature Electronics.

Robust analytical gate delay modeling for low voltage circuits

David Z. Pan, Anand Ramalingam, Anirudh Devgan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting

David Z. Pan, Biying Xu, Ming Su, 2018, ISPD.

Latch Modeling forStatistical Timing Analysis

David Z. Pan, Daifeng Wang, 2008 .

Sensitivity guided net weighting for placement-driven synthesis

David Z. Pan, Haoxing Ren, David S. Kung, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cross-level Monte Carlo framework for system vulnerability evaluation against fault attack

Meng Li, David Z. Pan, Vikas Chandra, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Triple patterning lithography (TPL) layout decomposition using end-cutting

David Z. Pan, Bei Yu, Jhih-Rong Gao, 2013, Advanced Lithography.

Fully Integrated 20 Gbit/s Silicon Optical Computing Chip for 4-Bit Full Adders

Ray T. Chen, David Z. Pan, Chenghao Feng, 2019, 2019 IEEE Photonics Conference (IPC).

UTPlaceF 2.0

Meng Li, David Z. Pan, Yibo Lin, 2018, ACM Trans. Design Autom. Electr. Syst..

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures

David Z. Pan, Meng Li, Bei Yu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A high-performance triple patterning layout decomposer with balanced density

David Z. Pan, Bei Yu, Yen-Hung Lin, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Automated logic synthesis for electro-optic computing in integrated photonics

Ray T. Chen, David Z. Pan, Chenghao Feng, 2019, OPTO.

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

David Z. Pan, Love Singhal, Saurabh N. Adya, 2017, ISPD.

O-Router: An optical routing framework for low power on-chip silicon nano-photonic integration

Ray T. Chen, David Z. Pan, Duo Ding, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography

Kun Yuan, Jae-Seok Yang, David Z. Pan, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Wafer Map Defect Patterns Classification using Deep Selective Learning

David Z. Pan, Mohamed Baker Alawieh, Duane Boning, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

On the Impossibility of Approximation-Resilient Circuit Locking

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues

Sani R. Nassif, Keith A. Bowman, David Z. Pan, 2012, 17th Asia and South Pacific Design Automation Conference.

Nanolithography and CAD challenges for 32nm/22nm and beyond

David Z. Pan, Vivek Singh, Stephen Renwick, 2008, ICCAD.

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks

David Z. Pan, Anand Rajaram, D. Pan, 2008, 2008 Asia and South Pacific Design Automation Conference.

Design for manufacturability and reliability in extreme-scaling VLSI

David Z. Pan, Xiaoqing Xu, Bei Yu, 2016, Science China Information Sciences.

Overlay aware interconnect and timing variation modeling for double patterning technology

Jae-Seok Yang, David Z. Pan, 2008, ICCAD 2008.

Evolving challenges and techniques for nanometer SoC clock network synthesis

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

FPGA Accelerated FPGA Placement

David Z. Pan, Love Singhal, Shounak Dhar, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

Interconnect design for deep submicron ICs

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Wire density driven global routing for CMP variation and timing

David Z. Pan, Minsik Cho, Ruchir Puri, 2006, ICCAD.

Sensitivity guided net weighting for placement-driven synthesis

David Z. Pan, Haoxing Ren, David S. Kung, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient DSA-DP hybrid lithography conflict detection and guiding template assignment

David Z. Pan, Brian Cline, Greg Yeric, 2017, Advanced Lithography.

CMP aware shuttle mask floorplanning

Gang Xu, David Z. Pan, Martin D. F. Wong, 2005, ASP-DAC.

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

ML for CAD - Where is the Treasure Hiding?

David Z. Pan, Marilyn Wolf, Raviv Gal, 2020, MLCAD.

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations

Derong Liu, David Z. Pan, Bei Yu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analysis techniques for nanometer digital integrated circuits

David Z. Pan, Anand Ramalingam, 2007 .

Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models

David Z. Pan, Mohamed Baker Alawieh, Sinead Williamson, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Machine learning for IC design and technology co-optimization in extreme scaling

David Z. Pan, 2018 .

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Nan Sun, David Z. Pan, Biying Xu, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Multi-Operand Directed Logic-Based Electro-Optic Gates for Ultracompact Optical Computing

David Z. Pan, Chenghao Feng, Zheng Zhao, 2019, 2019 IEEE Photonics Conference (IPC).

Electromigration-aware redundant via insertion

Jiwoo Pak, David Z. Pan, Bei Yu, 2015, The 20th Asia and South Pacific Design Automation Conference.

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network

David Z. Pan, Zheng Zhao, Mingjie Liu, 2020, MLCAD.

Toward Unidirectional Routing Closure in Advanced Technology Nodes

David Z. Pan, Xiaoqing Xu, D. Pan, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Process variation aware OPC with variational lithography modeling

David Z. Pan, Peng Yu, Sean X. Shi, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

David Z. Pan, Brucek Khailany, Yibo Lin, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions

David Z. Pan, Mohamed Baker Alawieh, Yibo Lin, 2019, Journal of Microelectronic Manufacturing.

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

Yang Li, David Z. Pan, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sleep transistor sizing using timing criticality and temporal currents

David Z. Pan, Bin Zhang, Anand Ramalingam, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Directed self-assembly cut mask assignment for unidirectional design

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2015 .

Machine learning based lithographic hotspot detection with critical-feature extraction and classification

David Z. Pan, Joydeep Ghosh, Duo Ding, 2009, 2009 IEEE International Conference on IC Design and Technology.

Total sensitivity based dfm optimization of standard library cells

David Z. Pan, Yongchan Ban, Savithri Sundareswaran, 2010, ISPD '10.

Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict

David Z. Pan, Biying Xu, Bei Yu, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

PARR: pin access planning and regular routing for self-aligned double patterning

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2015, DAC.

Chemical-mechanical polishing aware application-specific 3D NoC design

David Z. Pan, Wooyoung Jang, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Double patterning technology friendly detailed routing

David Z. Pan, Yongchan Ban, Minsik Cho, 2008, ICCAD 2008.

A3MAP: architecture-aware analytic mapping for networks-on-chip

David Z. Pan, Woo-Young Jang, 2010, ASP-DAC 2010.

Triple/quadruple patterning layout decomposition via linear programming and iterative rounding

Bei Yu, David Z. Pan, Ross Baldick, 2017 .

An integrated nonlinear placement framework with congestion and porosity aware buffer planning

David Z. Pan, Tung-Chieh Chen, Ashutosh Chakraborty, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

David Z. Pan, Biying Xu, Xiyuan Tang, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Voltage and frequency island optimizations for many-core/networks-on-chip designs

David Z. Pan, Duo Ding, Wooyoung Jang, 2010, The 2010 International Conference on Green Circuits and Systems.

Logic synthesis for energy-efficient photonic integrated circuits

Ray T. Chen, David Z. Pan, Zheng Zhao, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Fabrication and characterization of parallel-coupled dual racetrack silicon microresonators

Wei Jiang, David Z. Pan, Duo Ding, 2012, Other Conferences.

Design for Manufacturing With Emerging Nanolithography

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing

Ulf Schlichtmann, David Z. Pan, Bei Yu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Robust Chip-Level Clock Tree Synthesis

David Z. Pan, Anand Rajaram, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout decomposition of self-aligned double patterning for 2D random logic patterning

David Z. Pan, Yongchan Ban, Kevin Lucas, 2011, Advanced Lithography.

Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs

David Z. Pan, Ruchir Puri, Subhendu Roy, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A high-performance droplet router for digital microfluidic biochips

David Z. Pan, Minsik Cho, 2008, ISPD '08.

A new LP based incremental timing driven placement for high performance designs

David Z. Pan, Tao Luo, David Newmark, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist

David Z. Pan, Yier Jin, Yibo Lin, 2020, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction

David Z. Pan, Tetsuaki Matsunawa, Jhih-Rong Gao, 2015, Advanced Lithography.

Metal-Density-Driven Placement for CMP Variation and Routability

Yao-Wen Chang, David Z. Pan, Minsik Cho, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Total power optimization combining placement, sizing and multi-Vt through slack distribution management

David Z. Pan, Tao Luo, David Newmark, 2008, 2008 Asia and South Pacific Design Automation Conference.

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond

Naehyuck Chang, Yuan Xie, David Z. Pan, 2014, TODE.

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction

David Z. Pan, Yilin Zhang, Salim Chowdhury, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Lithography friendly routing: From construct-by-correction to correct-by-construction

David Z. Pan, Yongchan Ban, Minsik Cho, 2008 .

Standard cell pin access and physical design in advanced lithography

David Z. Pan, Xiaoqing Xu, Brian Cline, 2016, Advanced Lithography.

Detailed placement in advanced technology nodes: A survey

David Z. Pan, Bei Yu, Yibo Lin, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion

Bei Yu, David Z. Pan, Xiaoqing Xu, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Chemical-mechanical polishing aware application-specific 3D NoC design

Jae-Seok Yang, David Z. Pan, Ou He, 2011, ICCAD 2011.

UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing

David Z. Pan, Wuxi Li, Shounak Dhar, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Streak: Synergistic topology generation and route synthesis for on-chip performance-critical signal groups

Derong Liu, David Z. Pan, Duo Ding, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis

Derong Liu, Ray T. Chen, David Z. Pan, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008

David Z. Pan, Gi-Joon Nam, 2008, ISPD.

Pushing ASIC performance in a power envelope

Dennis Sylvester, John M. Cohn, David Z. Pan, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Physical hierarchy generation with routing congestion control

Jason Cong, David Z. Pan, Chin-Chih Chang, 2002, ISPD '02.

Improved crosstalk modeling for noise constrained interconnect optimization

Jason Cong, David Z. Pan, Prasanna V. Srinivas, 2001, ASP-DAC '01.

Hippocrates: First-Do-No-Harm Detailed Placement

David Z. Pan, Gi-Joon Nam, Charles J. Alpert, 2007, 2007 Asia and South Pacific Design Automation Conference.

Track Routing and Optimization for Yield

David Z. Pan, Minsik Cho, Ruchir Puri, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BoxRouter: ANewGlobal Router Basedon BoxExpansion andProgressive ILP

David Z. Pan, Minsik Cho, 2006 .

TILA: Timing-driven incremental layer assignment

Derong Liu, David Z. Pan, Bei Yu, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Subresolution Assist Feature Generation With Supervised Data Learning

Chikaaki Kodama, Toshiya Kotani, Shigeki Nojima, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A unified non-rectangular device and circuit simulation model for timing and power

David Z. Pan, Peng Yu, Sean X. Shi, 2006, ICCAD.

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

Nan Sun, David Z. Pan, Shaolan Li, 2018, IEEE Journal of Solid-State Circuits.

Fast lithography simulation under focus variations for OPC and layout optimizations

David Z. Pan, Chris A. Mack, Peng Yu, 2006, SPIE Advanced Lithography.

Application-Aware NoC Design for Efficient SDRAM Access

David Z. Pan, Woo-Young Jang, 2011, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SoulNet: ultrafast optical source optimization utilizing generative neural networks for advanced lithography

Yayi Wei, David Z. Pan, Lisong Dong, 2019 .

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

David Z. Pan, Shaolan Li, Zhichao Tan, 2020, IEEE Journal of Solid-State Circuits.

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing

Ulf Schlichtmann, David Z. Pan, Grace Li Zhang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment

David Z. Pan, Xiaoqing Xu, Joydeep Mitra, 2017, ISPD.

Redundant-via enhanced maze routing for yield improvement

Gang Xu, David Z. Pan, Li-Da Huang, 2005, ASP-DAC.

High-Definition Routing Congestion Prediction for Large-Scale FPGAs

David Z. Pan, Mohamed Baker Alawieh, Love Singhal, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Kun Yuan, David Z. Pan, Minsik Cho, 2007, ICCAD 2007.

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix) pdf

Ulf Schlichtmann, David Z. Pan, Bei Yu, 2020, ArXiv.

Metal-Density-Driven Placement for CMP Variation and Routability

Yao-Wen Chang, David Z. Pan, Minsik Cho, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Jiaqi Gu, David Z. Pan, Brucek Khailany, 2020 .

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement

David Z. Pan, Sean X. Shi, Ashutosh Chakraborty, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

David Z. Pan, Brian Cline, Greg Yeric, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction

Kun Yuan, David Z. Pan, Yongchan Ban, 2008, 2008 45th ACM/IEEE Design Automation Conference.

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Global Routing

David Z. Pan, Minsik Cho, 2016, Encyclopedia of Algorithms.

Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization - New findings on the layout dependent aging effects

Ru Huang, Shaofeng Yu, David Z. Pan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

MOSAIC: Mask optimizing solution with process window aware inverse correction

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Interconnect estimation and planning for deep submicron designs

Jason Cong, David Z. Pan, 1999, DAC '99.

BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP

David Z. Pan, Minsik Cho, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization pdf

David Z. Pan, Chenghao Feng, Zheng Zhao, 2020, ArXiv.

GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing

David Z. Pan, Duo Ding, Bei Yu, 2012, 17th Asia and South Pacific Design Automation Conference.

PADE: A high-performance placer with automatic datapath extraction and evaluation through high-dimensional data learning

David Z. Pan, Duo Ding, Samuel I. Ward, 2012, DAC Design Automation Conference 2012.

Skew Management of NBTI Impacted Gated Clock Trees

David Z. Pan, Ashutosh Chakraborty, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Wire sizing with scattering effect for nanoscale interconnection

David Z. Pan, Sean X. Shi, D. Pan, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Microresonator-based electro-optic full adder for optical computing in integrated photonics (Conference Presentation)

Ray T. Chen, David Z. Pan, Zheng Wang, 2018 .

Model-based guiding pattern synthesis for robust assembly of contact layers using directed self-assembly

David Z. Pan, Joydeep Mitra, Andres Torres, 2018 .

Lithography hotspot detection and mitigation in nanometer VLSI

David Z. Pan, Bei Yu, Jhih-Rong Gao, 2013, 2013 IEEE 10th International Conference on ASIC.

Skew Management of NBTI Impacted Gated Clock Trees

David Z. Pan, Ashutosh Chakraborty, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Machine learning and pattern matching in physical design

Xuan Zeng, David Z. Pan, Tetsuaki Matsunawa, 2015, The 20th Asia and South Pacific Design Automation Conference.

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning

Qiang Liu, David Z. Pan, Dilin Wang, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices

David Z. Pan, Sean X. Shi, Ashutosh Chakraborty, 2008, 2008 Design, Automation and Test in Europe.

Layout Decomposition for Triple Patterning

Bei Yu, David Z. Pan, 2016 .

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Kun Yuan, David Z. Pan, Minsik Cho, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Global interconnect sizing and spacing with consideration of coupling capacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Placement mitigation techniques for power grid electromigration

David Z. Pan, Xiaoqing Xu, Yongsheng Sun, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node

David Z. Pan, Xiaoqing Xu, Brian Cline, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Power and Accuracy Co-Optimization of an Optical Full Adder via Optimization Algorithms

David Z. Pan, Chenghao Feng, Zheng Zhao, 2019, 2019 IEEE Photonics Conference (IPC).

DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints

David Z. Pan, Jiaqi Gu, Yibo Lin, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Compact Design of on-Chip Elman Optical Recurrent Neural Network

Jiaqi Gu, David Z. Pan, Chenghao Feng, 2020, 2020 Conference on Lasers and Electro-Optics (CLEO).

Wavelength-division-multiplexing-based electronic-photonic network for high-speed computing (Conference Presentation)

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020 .

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Variation tolerant buffered clock network synthesis with cross links

David Z. Pan, Anand Rajaram, 2006, ISPD '06.

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2015, ACM Great Lakes Symposium on VLSI.

Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability

Ray T. Chen, David Z. Pan, Chenghao Feng, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout optimizations for double patterning lithography

David Z. Pan, Yongchan Ban, Jae-seok Yang, 2009, 2009 IEEE 8th International Conference on ASIC.

Interconnect performance estimation models for design planning

Jason Cong, David Z. Pan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

Meng Li, David Z. Pan, Yier Jin, 2017, ACM Great Lakes Symposium on VLSI.

Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices

David Z. Pan, Joydeep Mitra, Andres Torres, 2017, Advanced Lithography.

Self-aligned double patterning layout decomposition with complementary e-beam lithography

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

BOB-router: A new buffering-aware global router with over-the-block routing resources optimization

David Z. Pan, Yilin Zhang, Salim Chowdhury, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

David Z. Pan, Biying Xu, Bei Yu, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography

Bei Yu, David Z. Pan, Xiaoqing Xu, 2016 .

A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology

Nan Sun, David Z. Pan, Biying Xu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Manufacturability Aware Routing in Nanometer VLSI

David Z. Pan, Minsik Cho, Kun Yuan, 2010, Found. Trends Electron. Des. Autom..

Bridging the gap from mask to physical design for multiple patterning lithography

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2014, Advanced Lithography.

Machine Learning for Yield Learning and Optimization

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2018, 2018 IEEE International Test Conference (ITC).

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction

David Z. Pan, Peng Yu, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

LithoROC: lithography hotspot detection with explicit ROC optimization

Qiang Liu, Meng Li, David Z. Pan, 2019, ASP-DAC.

RegPlace: A high quality open-source placement framework for structured ASICs

David Z. Pan, Ashutosh Chakraborty, Anurag Kumar, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Stitch aware detailed placement for multiple e-beam lithography

David Z. Pan, Charles J. Alpert, Zhuo Li, 2016, ASP-DAC.

Challenges and opportunities toward fully automated analog layout design

Hao Chen, David Z. Pan, Xiyuan Tang, 2020 .

Simultaneous statistical delay and slew optimization for interconnect pipelines

David Z. Pan, Andrew Havlir, D. Pan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Detailed placement for modern FPGAs using 2D dynamic programming

David Z. Pan, Love Singhal, Saurabh N. Adya, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation

David Z. Pan, Peng Yu, YU Peng, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Practical public PUF enabled by solving max-flow problem on chip

Meng Li, David Z. Pan, Kai Zhong, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

PASAP: Power aware structured ASIC placement

David Z. Pan, Ashutosh Chakraborty, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

David Z. Pan, Xiaoqing Xu, Wen-Hao Liu, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Layout Decomposition for Triple Patterning

David Z. Pan, Bei Yu, D. Pan, 2016, Encyclopedia of Algorithms.

Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints

David Z. Pan, Yilin Zhang, 2014, ISPD '14.

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Low-power integration of on-chip nanophotonic interconnect for high-performance optoelectrical IC

David Z. Pan, Duo Ding, 2012, Other Conferences.

True process variation aware optical proximity correction with variational lithography modeling and model calibration

David Z. Pan, Sean X. Shi, Peng Yu, 2007 .

CAD for double patterning lithography

Jae-Seok Yang, David Z. Pan, Kun Yuan, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Integrated WDM-Based Optical Comparator for High-Speed Computing

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 Conference on Lasers and Electro-Optics (CLEO).

Double patterning technology friendly detailed routing

David Z. Pan, Yongchan Ban, Minsik Cho, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

10^6 Channel parallelism Fourier-optic convolutional filter and neural network processor

Mario Miscuglio, Zibo Hu, Shurui Li, 2020 .

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Model-based guiding pattern synthesis for on-target and robust assembly of via and contact layers using DSA

David Z. Pan, Joydeep Mitra, Andres Torres, 2017, Advanced Lithography.

Manufacturability-Aware Routing

David Z. Pan, Joydeep Mitra, Minsik Cho, 2008, Handbook of Algorithms for Physical Design Automation.

Latch Modeling for Statistical Timing Analysis

David Z. Pan, Anand Ramalingam, Sean X. Shi, 2008, 2008 Design, Automation and Test in Europe.

DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective

David Z. Pan, Tao Luo, 2007, Modern Circuit Placement.

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- $\Delta\Sigma$ M Structure

David Z. Pan, Shaolan Li, Biying Xu, 2020, IEEE Journal of Solid-State Circuits.

Computational geometry based placement migration

David Z. Pan, Charles J. Alpert, Tao Luo, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Stitch aware detailed placement for multiple e-beam lithography

David Z. Pan, Charles J. Alpert, Zhuo Li, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Synthesis of variation tolerant clock distribution networks

David Z. Pan, Anand Rajaram, D. Pan, 2008 .

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability

Kun Yuan, David Z. Pan, Minsik Cho, 2009, TODE.

Modeling of electromigration in through-silicon-via based 3D IC

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

True crosstalk aware incremental placement with noise map

David Z. Pan, Haoxing Ren, P. G. Villarubia, 2004, ICCAD 2004.

E-BLOW: E-beam lithography overlapping aware stencil planning for MCC system

Kun Yuan, David Z. Pan, Jhih-Rong Gao, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Interconnect delay estimation models for synthesis and design planning

Jason Cong, David Z. Pan, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint

David Z. Pan, Joon-Sung Yang, Taehee Lee, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analysis and optimization of NBTI induced clock skew in gated clock trees

David Z. Pan, Anand Rajaram, Ashutosh Chakraborty, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Automatic Selection of Structure Parameters of Silicon on Insulator Lateral Power Device Using Bayesian Optimization

David Z. Pan, Mohamed Baker Alawieh, Yibo Lin, 2020, IEEE Electron Device Letters.

Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007

David Z. Pan, Patrick H. Madden, 2007, ISPD.

TimingSAT: Decamouflaging Timing-based Logic Obfuscation

Meng Li, David Z. Pan, Yier Jin, 2018, 2018 IEEE International Test Conference (ITC).

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks

David Z. Pan, Mohamed Baker Alawieh, Yibo Lin, 2020, IEEE Access.

MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis

David Z. Pan, Anand Rajaram, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Controlling NBTI degradation during static burn-in testing

David Z. Pan, Ashutosh Chakraborty, D. Pan, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing

Yih-Lang Li, David Z. Pan, Yongchan Ban, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Robust chip-level clock tree synthesis for SOC designs

David Z. Pan, Anand Rajaram, D. Pan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Accurate lithography hotspot detection based on principal component analysis-support vector machine classifier with hierarchical data clustering

Bei Yu, Xuan Zeng, David Z. Pan, 2014 .

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014

Bernd Becker, Matthias Sauer, Ansuman Banerjee, 2014, VLSI Design.

Standard Cell Compliance and Placement Co-Optimization

Bei Yu, David Z. Pan, 2016 .

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Methodology for standard cell compliance and detailed placement for triple patterning lithography

David Z. Pan, Xiaoqing Xu, Bei Yu, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Provably Secure Camouflaging Strategy for IC Protection

Meng Li, David Z. Pan, Zheng Zhao, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation

David Z. Pan, Joydeep Ghosh, Duo Ding, 2012, 17th Asia and South Pacific Design Automation Conference.

OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture

David Z. Pan, Duo Ding, D. Pan, 2009, SLIP '09.

Diffusion-Based Placement Migration With Application on Legalization

David Z. Pan, Gi-Joon Nam, Charles J. Alpert, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Session details: Keynote address

David Z. Pan, 2008, ISPD '08.

Breakdown Voltage Prediction of SOI Lateral Power Device Using Deep Neural Network

David Z. Pan, Yufeng Guo, Mohamed Baker Alawieh, 2019, 2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC).

Session details: Crosstalk noise avoidance and power/ground network optimization

Dennis Sylvester, David Z. Pan, 2005, ASP-DAC '05.

Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

David Z. Pan, Jian Chen, Anand Rajaram, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography

Hai Zhou, Xuan Zeng, David Z. Pan, 2015, ACM Trans. Design Autom. Electr. Syst..

DNA Microarray placement for improved performance and reliability

David Z. Pan, Minsik Cho, Anurag Kumar, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

ISPD placement contest updates and ISPD 2007 global routing contest

David Z. Pan, Gi-Joon Nam, Patrick H. Madden, 2007, ISPD '07.

Sequential Logic and Pipelining in Chip-Based Electronic-Photonic Digital Computing

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, IEEE Photonics Journal.

S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits

David Z. Pan, Mohamed Baker Alawieh, Xiyuan Tang, 2019, ASP-DAC.

IC Camouflaging Optimization and Evaluation

Meng Li, David Z. Pan, D. Pan, 2020 .

Practical Split Manufacturing Optimization

Meng Li, David Z. Pan, D. Pan, 2020 .

Hardware-software co-design of slimmed optical neural networks

Derong Liu, Meng Li, Ray T. Chen, 2019, ASP-DAC.

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs

David Z. Pan, Brucek Khailany, Yibo Lin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

David Z. Pan, Minsik Cho, Minsik Cho, 2008, 2008 Asia and South Pacific Design Automation Conference.

Structure-Aware Placement Techniques for Designs With Datapaths

Earl E. Swartzlander, David Z. Pan, Natarajan Viswanathan, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A voltage-frequency island aware energy optimization framework for networks-on-chip

David Z. Pan, Duo Ding, Woo-Young Jang, 2008, ICCAD 2008.

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

David Z. Pan, Minsik Cho, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Timing-Driven Placement

David Z. Pan, Haoxing Ren, Bill Halpin, 2008, Handbook of Algorithms for Physical Design Automation.

Guest Editorial

David Z. Pan, Patrick H. Madden, P. Madden, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

OpenMPL: An Open Source Layout Decomposer pdf

David Z. Pan, Qi Sun, Iris Hui-Ru Jiang, 2018, ArXiv.

TRIAD: A triple patterning lithography aware detailed router

Yih-Lang Li, David Z. Pan, Bei Yu, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Voltage-Frequency Island aware energy optimization framework for networks-on-chip

David Z. Pan, Duo Ding, Wooyoung Jang, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography

David Z. Pan, Yongchan Ban, 2010, Design Automation Conference.

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Hai Zhou, Xuan Zeng, David Z. Pan, 2016, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On-chip Microring Resonator Based Electro-optic Full Adder for Optical Computing

Ray T. Chen, David Z. Pan, Zheng Wang, 2017, CLEO 2017.

A multi-objective floorplanner for shuttle mask optimization

Gang Xu, David Z. Pan, Martin D. F. Wong, 2004, SPIE Photomask Technology.

A New Paradigm for FPGA Placement Without Explicit Packing

David Z. Pan, Wuxi Li, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Tackling signal electromigration with learning-based detection and multistage mitigation

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2019, ASP-DAC.

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

Nan Sun, David Z. Pan, Xiaoqing Xu, 2017, ISPD.

A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip

David Z. Pan, Wooyoung Jang, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

AppSAT: Approximately deobfuscating integrated circuits

Meng Li, David Z. Pan, Yier Jin, 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study

Jae-Seok Yang, Sung Kyu Lim, David Z. Pan, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Machine Learning in Physical Verification, Mask Synthesis, and Physical Design

David Z. Pan, Yibo Lin, D. Pan, 2019, Machine Learning in VLSI Computer-Aided Design.

Improved algorithms for link-based non-tree clock networks for skew variability reduction

Jiang Hu, David Z. Pan, Anand Rajaram, 2005, ISPD '05.

True crosstalk aware incremental placement with noise map

David Z. Pan, Paul G. Villarrubia, Haoxing Ren, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

Sung Kyu Lim, David Z. Pan, Moongon Jung, 2012, DAC Design Automation Conference 2012.

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce

David Z. Pan, Anand Ramalingam, Anirudh Devgan, 2007, J. Low Power Electron..

Guest Editorial

David Z. Pan, Gi-Joon Nam, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Application-Aware NoC Design for Efficient SDRAM Access

David Z. Pan, Wooyoung Jang, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault Attack Protection and Evaluation

Meng Li, David Z. Pan, 2020 .

Semisupervised Hotspot Detection With Self-Paced Multitask Learning

Yayi Wei, David Z. Pan, Yibo Lin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clustering

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2014, Advanced Lithography.

An SDRAM-aware router for Networks-on-Chip

David Z. Pan, Wooyoung Jang, 2009, 2009 46th ACM/IEEE Design Automation Conference.

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

Nan Sun, David Z. Pan, Wei Shi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Provably secure camouflaging strategy for IC protection

Meng Li, David Z. Pan, Yier Jin, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Accurate power grid analysis with behavioral transistor network modeling

David Z. Pan, Anand Ramalingam, Giri Devarayanadurg, 2007, ISPD '07.

Overlay aware interconnect and timing variation modeling for Double Patterning Technology

Jae-Seok Yang, David Z. Pan, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout

Nan Sun, David Z. Pan, Biying Xu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3-D ICs

Xuan Zeng, David Z. Pan, Hengliang Zhu, 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Design for Manufacturability with Advanced Lithography

David Z. Pan, Bei Yu, 2015 .

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

David Z. Pan, Bei Yu, Brian Cline, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Efficient Training Framework for Reversible Neural Architectures

Jiaqi Gu, David Z. Pan, Zixuan Jiang, 2020, ECCV.

Buffer block planning for interconnect-driven floorplanning

Jason Cong, David Z. Pan, Tianming Kong, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Enhanced DCT2-based inverse mask synthesis with initial SRAF insertion

David Z. Pan, Peng Yu, Shanhu Shen, 2008, Photomask Technology.

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII

Hao Chen, David Z. Pan, Shaolan Li, 2020, IEEE Design & Test.

PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control pdf

Meng Li, David Z. Pan, Vikas Chandra, 2017, ArXiv.

Synergistic modeling and optimization for nanometer IC design/manufacturing integration

David Z. Pan, 2008, SBCCI '08.

Incremental Layer Assignment Driven by an External Signoff Timing Engine

Derong Liu, David Z. Pan, Xiaoqing Xu, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures

David Z. Pan, Navid Khoshavi, Yu Bi, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Lithography hotspot detection using a double inception module architecture

Jing Chen, David Z. Pan, Mohamed Baker Alawieh, 2019 .

Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Giovanni De Micheli, David Z. Pan, Thomas Ernst, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

A systematic framework for evaluating standard cell middle-of-line (MOL) robustness for multiple patterning

Bei Yu, David Z. Pan, Xiaoqing Xu, 2015, Advanced Lithography.

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

Xi Liu, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

OPERON: optical-electrical power-efficient route synthesis for on-chip signals

Derong Liu, Ray T. Chen, David Z. Pan, 2018, DAC.

IP Protection and Supply Chain Security through Logic Obfuscation

David Z. Pan, Yier Jin, Kaveh Shamsi, 2019, ACM Trans. Design Autom. Electr. Syst..

Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk)

David Z. Pan, Mohamed Baker Alawieh, Wei Ye, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding

Bei Yu, David Z. Pan, Xiaoqing Xu, 2016, SPIE Advanced Lithography.

Exploration of VLSI CAD researches for early design rule evaluation

David Z. Pan, Kevin Lucas, Chul-Hong Park, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs

Jiwoo Pak, Sung Kyu Lim, David Z. Pan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions

Derong Liu, David Z. Pan, Subhendu Roy, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints

Bei Yu, David Z. Pan, Yibo Lin, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Microdisk-Based Full Adders for Optical Computing in Silicon Photonics

Ray T. Chen, David Z. Pan, Richard Soref, 2018, 2018 Conference on Lasers and Electro-Optics (CLEO).

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection

Meng Li, David Z. Pan, Mohamed Baker Alawieh, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

PEAKASO: peak-temperature aware scan-vector optimization

David Z. Pan, Minsik Cho, 2006, 24th IEEE VLSI Test Symposium.

Accurate thermal analysis considering nonlinear thermal conductivity

Sani R. Nassif, David Z. Pan, Anand Ramalingam, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

L-shape based layout fracturing for e-beam lithography

David Z. Pan, Jhih-Rong Gao, Bei Yu, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown

David Z. Pan, Subhendu Roy, D. Pan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Revisit sequential logic obfuscation: Attacks and defenses

David Z. Pan, Shaojie Zhang, Yier Jin, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Pyramids: an efficient computational geometry-based approach for timing-driven placement

Tao Luo, David Z. Pan, Charles J. Alpert, 2008, ICCAD 2008.

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation

Hai Zhou, Xuan Zeng, David Z. Pan, 2017, ACM Trans. Design Autom. Electr. Syst..

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups

Derong Liu, David Z. Pan, Duo Ding, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond

David Z. Pan, Peter Debacker, Praveen Raghavan, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Layout compliance for triple patterning lithography: an iterative approach

Bei Yu, David Z. Pan, Gilda Garreton, 2014, Photomask Technology.

Pushing multiple patterning in sub-10nm: Are we ready?

David Z. Pan, Xiaoqing Xu, Lars Liebmann, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Machine learning for IC design and technology co-optimization in extreme scaling

David Z. Pan, 2018, VLSI-DAT.

UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper)

Meng Li, David Z. Pan, Jiajun Wang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Novel binary linear programming for high performance clock mesh synthesis

David Z. Pan, Minsik Cho, Ruchir Puri, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Toward metrics of design automation research impact

Andrew B. Kahng, David Z. Pan, Siddhartha Nath, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Toward Metrics of Design Automation Research Impact ( invited paper )

Andrew B. Kahng, David Z. Pan, Siddhartha Nath, 2015 .

SOCS based post-layout optimization for multiple patterns with light interference prediction

Shigeki Nojima, David Z. Pan, Tetsuaki Matsunawa, 2017, Advanced Lithography.

Optical proximity correction with hierarchical Bayes model

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2016 .

Nanolithography and CAD challenges for 32nm/22nm and beyond

David Z. Pan, Vivek Singh, Stephen Renwick, 2008, ICCAD 2008.

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)

David Z. Pan, Sri Parameswaran, R. Iris Bahar, 2018, IEEE Des. Test.

Optical switches based carry-ripple adder for future highspeed and low-power consumption optical computing

Zheng Wang, Ray T. Chen, David Z. Pan, 2017, 2017 Conference on Lasers and Electro-Optics (CLEO).

S 2 -PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.

David Z. Pan, Mohamed Baker Alawieh, Xiyuan Tang, 2019, ASP-DAC 2019.

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Shigeki Nojima, Meng Li, David Z. Pan, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analysis of Microresonator-Based Logic Gate for High-Speed Optical Computing in Integrated Photonics

Ray T. Chen, David Z. Pan, Chenghao Feng, 2020, IEEE Journal of Selected Topics in Quantum Electronics.

GDP: GPU accelerated Detailed Placement

David Z. Pan, Shounak Dhar, 2018, 2018 IEEE High Performance extreme Computing Conference (HPEC).

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning

Shigeki Nojima, David Z. Pan, Mohamed Baker Alawieh, 2020, ISPD.

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Kun Yuan, Jae-Seok Yang, David Z. Pan, 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?

Meng Li, David Z. Pan, Yier Jin, 2017, ACM Great Lakes Symposium on VLSI.

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction

David Z. Pan, Deming Chen, Chen-Hsuan Lin, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

TROY: Track Router with Yield-driven Wire Planning

David Z. Pan, Minsik Cho, Ruchir Puri, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Multilevel global placement with congestion control

Jason Cong, David Z. Pan, Xin Yuan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow

Hao Chen, David Z. Pan, Xiyuan Tang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation

Meng Li, David Z. Pan, Yier Jin, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Massive parallelism Fourier-optic convolutional processor

Mario Miscuglio, Zibo Hu, Shurui Li, 2020 .

BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP

David Z. Pan, Minsik Cho, Minsik Cho, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

OpenMPL: An Open Source Layout Decomposer: Invited Paper

David Z. Pan, Qi Sun, Wei Li, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

Hybrid hotspot detection using regression model and lithography simulation

Shigeki Nojima, David Z. Pan, Tetsuaki Matsunawa, 2016, SPIE Advanced Lithography.

Layout Decomposition for Other Patterning Techniques

Bei Yu, David Z. Pan, D. Pan, 2016 .

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning

Xuan Zeng, David Z. Pan, Hengliang Zhu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

AENEID: A generic lithography-friendly detailed router based on post-RET data learning and hotspot detection

Kun Yuan, David Z. Pan, Jhih-Rong Gao, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Reliability-aware global routing under thermal considerations

David Z. Pan, Katrina Lu, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion

Meng Li, David Z. Pan, Xiaoqing Xu, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Machine learning for mask/wafer hotspot detection and mask synthesis

David Z. Pan, Xiaoqing Xu, Yibo Lin, 2017, Photomask Technology.

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

David Z. Pan, Deming Chen, Keith A. Campbell, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A novel unified dummy fill insertion framework with SQP-based optimization method

Xuan Zeng, David Z. Pan, Changhao Yan, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Redundant Local-Loop Insertion for Unidirectional Routing

David Z. Pan, Xiaoqing Xu, Brian Cline, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures

David Z. Pan, Ruchir Puri, Subhendu Roy, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High performance lithographic hotspot detection using hierarchically refined machine learning

Fedor G. Pikus, David Z. Pan, Duo Ding, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters

Kun Yuan, David Z. Pan, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Electronic-photonic arithmetic logic unit for high-speed computing

Jiaqi Gu, David Z. Pan, Chenghao Feng, 2020, Nature Communications.

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning

David Z. Pan, Jhih-Rong Gao, 2012, ISPD '12.

RADAR: RET-aware detailed routing using fast lithography simulations

David Z. Pan, Joydeep Mitra, Peng Yu, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Laplacian eigenmaps- and Bayesian clustering-based layout pattern sampling and its applications to hotspot detection and optical proximity correction

David Z. Pan, Tetsuaki Matsunawa, Bei Yu, 2016 .

TACO: temperature aware clock-tree optimization

David Z. Pan, Minsik Cho, Suhail Ahmed, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell

Yunfei Deng, David Z. Pan, Harry J. Levinson, 2010, Advanced Lithography.

Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP

David Z. Pan, Jianli Chen, Wenxing Zhu, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning

J. Andres Torres, David Z. Pan, Duo Ding, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optical computing on silicon-on-insulator-based photonic integrated circuits

Ray T. Chen, David Z. Pan, Zheng Zhao, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Power Grid Reduction by Sparse Convex Optimization

Meng Li, David Z. Pan, Kai Zhong, 2018, ISPD.

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

David Z. Pan, Minsik Cho, Minsik Cho, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A shape-driven spreading algorithm using linear programming for global placement

David Z. Pan, Love Singhal, Shounak Dhar, 2019, ASP-DAC.

PARR: Pin access planning and regular routing for self-aligned double patterning

David Z. Pan, Xiaoqing Xu, Jhih-Rong Gao, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks

David Z. Pan, Mohamed Baker Alawieh, Meng Li, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout-dependent aging mitigation for critical path timing

Meng Li, David Z. Pan, Xiaoqing Xu, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Application-Aware NoC Design for Efficient

David Z. Pan, Woo-Young Jang, 2011 .

A novel intensity based optical proximity correction algorithm with speedup in lithography simulation

David Z. Pan, Peng Yu, 2007, ICCAD 2007.

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Device Layer-Aware Analytical Placement for Analog Circuits

Nan Sun, Derong Liu, David Z. Pan, 2019, ISPD.

Concurrent pin access optimization for unidirectional routing

David Z. Pan, Xiaoqing Xu, Vinicius S. Livramento, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization

Jason Cong, Xin Yuan, David Z. Pan, 2001 .

Incremental layer assignment for critical path timing

Derong Liu, David Z. Pan, Bei Yu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design

David Z. Pan, Yongchan Ban, 2014 .

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Kun Yuan, Jae-Seok Yang, David Z. Pan, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Clock power minimization using structured latch templates and decision tree induction

David Z. Pan, Natarajan Viswanathan, Charles J. Alpert, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Partial Functional Manipulation Based Wirelength Minimization

David Z. Pan, Avijit Dutta, D. Pan, 2006, 2006 International Conference on Computer Design.

An SDRAM-Aware Router for Networks-on-Chip

David Z. Pan, Woo-Young Jang, 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography

David Z. Pan, Bei Yu, Jiaojiao Ou, 2016, ISPD.

UNISM: Unified Scheduling and Mapping for General Networks on Chip

David Z. Pan, Sheqin Dong, Jinian Bian, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Electro-Optic Ripple-Carry Adder in Integrated Silicon Photonics for Optical Computing

Richard A. Soref, Ray T. Chen, David Z. Pan, 2018, IEEE Journal of Selected Topics in Quantum Electronics.

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

David Z. Pan, Linxiao Shen, Xiyuan Tang, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction

Kun Yuan, David Z. Pan, Yongchan Ban, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper

Nan Sun, David Z. Pan, Shaolan Li, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures

Meng Li, David Z. Pan, Yier Jin, 2018, ACM Great Lakes Symposium on VLSI.

Proceedings of the International Symposium on Physical Design: Foreword

David Z. Pan, Gi Joon Nam, 2008, ISPD 2008.

On stress aware active area sizing, gate sizing, and repeater insertion

David Z. Pan, Ashutosh Chakraborty, 2009, ISPD '09.

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization

Xuan Zeng, Fan Yang, David Z. Pan, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, ACM Great Lakes Symposium on VLSI.

WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography

Kun Yuan, David Z. Pan, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization

David Z. Pan, Yongchan Ban, D. Pan, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).

elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs

David Z. Pan, Yibo Lin, Wuxi Li, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Nan Sun, David Z. Pan, Jaydeep P. Kulkarni, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

Nan Sun, David Z. Pan, Wei Shi, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks

David Z. Pan, Yibo Lin, Mingjie Liu, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization

Ray T. Chen, David Z. Pan, Chenghao Feng, 2020, AAAI.

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

David Z. Pan, Brucek Khailany, Haoxing Ren, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, ArXiv.

Interactive Analog Layout Editing with Instant Placement Legalization

David Z. Pan, Yibo Lin, Mingjie Liu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation pdf

David Z. Pan, Dilin Wang, Hyoukjun Kwon, 2021, 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators

Ray T. Chen, David Z. Pan, Chenghao Feng, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, 2021 IEEE/CVF International Conference on Computer Vision (ICCV).

O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands

Jiaqi Gu, Ray T. Chen, David Z. Pan, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection

David Z. Pan, Mohamed Baker Alawieh, 2021, 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD).

Optimizer Fusion: Efficient Training with Better Locality and Parallelism pdf

David Z. Pan, Jiaqi Gu, Zixuan Jiang, 2021, ArXiv.

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks

David Z. Pan, Chandramouli V. Kashyap, Prateek Bhansali, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits pdf

David Z. Pan, Frederic T. Chong, Song Han, 2021, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Jiaqi Gu, David Z. Pan, Brucek Khailany, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization pdf

David Z. Pan, Chenghao Feng, Zixuan Jiang, 2021, NeurIPS.

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler

Nan Sun, David Z. Pan, Xiyuan Tang, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

Nan Sun, David Z. Pan, Mingjie Liu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Silicon photonic subspace neural chip for hardware-efficient deep learning pdf

David Z. Pan, Chenghao Feng, Zhoufeng Ying, 2021, ArXiv.

RoQNN: Noise-Aware Training for Robust Quantum Neural Networks pdf

David Z. Pan, Frederic T. Chong, Song Han, 2021, ArXiv.

TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction

David Z. Pan, Peng Yu, 2007, ICCAD 2007.

High Performance Lithography Hotspot Detection with Hierarchically Refined Machine Learning Methods

Fedor G. Pikus, David Z. Pan, Duo Ding, 2010 .

Large Scale Placement with Explicit Cell Movement Control

David Z. Pan, Tao Luo, 2006 .

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations

David Z. Pan, Harry J. Levinson, Yongchan Ban, 2010 .

A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

David Z. Pan, Moongon Jung, Suk-Kyu Ryu, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

What is double patterning lithography and its impact on nanometer design?

David Z. Pan, 2009, SIGD.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

Ru Huang, David Z. Pan, Xiaobo Jiang, 2013, IEEE Transactions on Electron Devices.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

David Z. Pan, Yongchan Ban, Savithri Sundareswaran, 2010 .

Triple patterning in 10nm node metal lithography

David Z. Pan, Kevin Lucas, Chris Cork, 2012 .