S. Saravanan

发表

A Novel DVS Algorithm for Real Time Embedded Operating Systems

A. Chilambuchelvan, S. Saravanan, J.R.P. Perinbam, 2009 .

Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications

M. Madheswaran, S. Saravanan, 2010 .

Design of low power multiplier with reduced spurious transition activity technique for wireless sensor network

M. Madheswaran, S. Saravanan, 2008, 2008 Fourth International Conference on Wireless Communication and Sensor Networks.

Run-Length Based Efficient Compression for System-on-Chip

S. Saravanan, Har Narayan Upadhyay, A. Balasubram, 2013 .

Low Power Spatial Modulation Scheme for Wide Band Multiple Input and Multiple Output Wireless Communication Systems

S. Saravanan, Har Narayan Upadhyay, Dhirendra Kumar Tripathi, 2012 .

Design of low power, high performance area efficient shannon based adder cell for neural network training

M. Madheswaran, S. Saravanan, 2009, 2009 International Conference on Control, Automation, Communication and Energy Conservation.

DESIGN AND ANALYSIS OF LOW POWER MULTIPLY AND ACCUMULATE UNIT USING PIXEL PROPERTIES REUSABILITY TECHNIQUE FOR IMAGE PROCESSING SYSTEMS

M. Madheswaran, S. Saravanan, 2012 .

Transition Vector Reduction using Segmentation method based on Compression Technique

S. Saravanan, Har Narayan Upadhyay, 2011 .

Certain investigations on energy saving techniques using DVS for low power embedded system

J. Raja Paul Perinbam, B. Chidhambararajan, A. Chilambuchelvan, 2006 .

Performance Analysis of DVS Algorithms for Reducing Processor Energy Consumption

S. Saravanan, J.R.P. Perinbam, A. Chilambuchelvan, 2007, International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007).

Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and low power 0.13µm adder for DSP block in wireless sensor node

M. Madheswaran, S. Saravanan, 2010, 2010 International Conference on Wireless Communication and Sensor Computing (ICWCSC).

Adapting Scan Based Test Vector for Compression Method Based On Transition Technique

S. Saravanan, Har Narayan Upadhyay, 2012 .

A SIMULATION SOFTWARE DEVELOPMENT FOR PERFORMANCE ANALYSIS OF DVS ALGORITHM FOR LOW POWER EMBEDDED SYSTEM

A. Chilambuchelvan, S. Saravanan, J. Raja, 2007 .

Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design

S. Saravanan, Har Narayan Upadhyay, 2012 .

Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern

S. Saravanan, Har Narayan Upadhyay, 2012 .

FSM-Based VLSI Architecture for the 3 × 3 Window-Based DBUTMPF Algorithm

G. Nagarajan, K. Vasanth, S. Saravanan, 2016 .

ENTROPY ANALYSIS FOR ACHIEVING HIGH COMPRESSION RATIO

S. Saravanan, Har Narayan Upadhyay, R. Silambamuthan, 2011 .