D. Jackuline Moni

发表

A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC

D. S. Shylu, S. Jasmine, D. Jackuline Moni, 2018, 2018 4th International Conference on Devices, Circuits and Systems (ICDCS).

An ultra low power 8 bit SAR ADC suitable for wireless medical applications

D. Jackuline Moni, K. Babita Diana, 2014, 2014 International Conference on Communication and Signal Processing.

Designing an average 8T SRAM

D. Jackuline Moni, Shyami Govind, 2014, 2014 International Conference on Communication and Signal Processing.

A LOW POWER CMOS ELECTROCARDIOGRAM AMPLIFIER DESIGN USING 0.18µM CMOS TECHNOLOGY

D. Jackuline Moni, N. Gopalakrishnan, 2013 .

Noiseless MOS parametric amplification in pipeline ADC

D. S. Shylu, D. Jackuline Moni, D. David Rajendra Prasad, 2011, 2011 3rd International Conference on Electronics Computer Technology.

Asynchronous successive approximation ADC for wireless applications in 180 nm CMOS technology

D. Jackuline Moni, K. Karthika Varthini, 2014, 2014 International Conference on Communication and Signal Processing.

Low power and high speed level shifters in 0.18um technology

D. Jackuline Moni, Om Prakash Kumar, Flavia Princess, 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

Design of ADC for ECG Applications using 0.18μM CMOS Technology

D. Jackuline Moni, H. Victor Du John, 2013 .

Design of DPSK modulator, demodulator and power telemetry for Epi-retinal and neural prostheses

D. Jackuline Moni, Saju George, 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

High flat gain low noise neural signal recording amplifier

D. Jackuline Moni, Sarin Vijay Mythry, 2017, 2017 International Conference on Signal Processing and Communication (ICSPC).

Design of RF front end receiver for biomedical applications

D. Jackuline Moni, X. SereneSanchia, 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

A 10-bit 40MS/s low power SHA-less pipelined ADC for system-on-chip digital TV application

D. S. Shylu, D. Jackuline Moni, T. Renita Pearlin, 2016, 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS).

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

P. Sam Paul, D. S. Shylu, D. Jackuline Moni, 2020 .

Design and simulation of asynchronous level crossing ADC using feedback DAC

D. Jackuline Moni, Anita Antony, Shobha Rekh Paulson, 2017, 2017 International Conference on Signal Processing and Communication (ICSPC).

A bulk-driven, buffer-biased, gain-boosted amplifier for biomedical signal enhancement

D. Jackuline Moni, Sarin Vijay Mythry, 2019 .

Design of 10b SAR ADC for biomedical applications

D. Jackuline Moni, Shilpa Maria Jose, 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

DESIGN AND ANALYSIS OF LOW POWER PSEUDO DIFFERENTIAL CLASS-AB TELESCOPIC OPERATIONAL AMPLIFIER

D. S. Shylu, D. Jackuline Moni, Neenu Brigit Francis, 2014 .

Design of low power and high speed configurable booth multiplier

D. Jackuline Moni, P. Eben Sophia, 2011, 2011 3rd International Conference on Electronics Computer Technology.

Radio Frequency Identification and Sensor Networks based Bin Level Monitoring Systems-A Review

S. R. Jino Ramson, Ranjeet Kumar, D. Jackuline Moni, 2018, 2018 4th International Conference on Devices, Circuits and Systems (ICDCS).

DESIGN OF CMOS-BASED 256 CHANNEL RETINAL STIMULATOR

D. Jackuline Moni, J. David Gnanaraj Blessing, 2013 .

High-speed and low-power dynamic latch comparator

D. Jackuline Moni, P. Jisha, 2012, 2012 International Conference on Devices, Circuits and Systems (ICDCS).

A novel study and research on multilayer AlAs/GaAs quantum dot inner layer for solar cell applications

D. Jackuline Moni, H. Victor Du John, G. Prabhu Rubesh, 2021, Int. J. Comput. Aided Eng. Technol..

Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET

D. Jackuline Moni, D. Nirmal, D. Gracia, 2022, Microelectron. J..

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

D. Jackuline Moni, D. Nirmal, Shylu Sam, 2021 .