F. Dosseul

3-D finite elements simulation of drop test reliability on a Chip Scale Package: Focus on the component architecture and materials

A. Bouchou, S. Belhenini, F. Dosseul, 2012, 2012 13th International Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

Full integration of a 3D demonstrator with TSV first interposer, ultra thin die stacking and wafer level packaging

N. Launay, G. Pares, A. Attard, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.