Soo-Ho Shin

Novel Cell Architecture for High Performance of 512-Mb DRAM with 0.12-µm Design Rule

Kinam Kim, Ju-Yong Lee, Min-Sang Kim, 2002 .

Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60㎚ Feature Sized DRAM

Seung-Chul Yang, Soo-Ho Shin, Tae-Young Chung, 2006 .

Highly manufacturable 4Gb DRAM using 0.11μm DRAM technology

Yoon-Soo Chun, Soo-Ho Shin, Y. Hwang, 2000 .

Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

Ju-Yong Lee, Kinam Kim, Seung-Chul Yang, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A highly reliable 1T/1C ferroelectric memory

Yoon-Soo Chun, Kinam Kim, Dong-won Shin, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

Gwan-Hyeob Koh, Hyung Soo Uh, Dae-Won Ha, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).