Jong-Kai Lin

Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

Xiaowu Zhang, F. X. Che, Jong-Kai Lin, 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

Stress Analysis and Design Optimization for Low- $k$ Chip With Cu Pillar Interconnection

Xiaowu Zhang, Jong-Kai Lin, K. Y. Au, 2015, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip

F. X. Che, Jong-Kai Lin, K. Y. Au, 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

Heterogeneous system implementation using through-silicon interposer (TSI) technology

Jun Zhou, Roshan Weerasekera, Ka Fai Chang, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).