Lars Braun

发表

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

Klaus D. Müller-Glaser, Oliver Sander, Benjamin Glas, 2012, Int. J. Reconfigurable Comput..

Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems

Lars Braun, 2013 .

Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space

Klaus D. Müller-Glaser, Oliver Sander, Benjamin Glas, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs

Lars Braun, Jürgen Becker, Walter Stechele, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

Lars Braun, Jürgen Becker, Michael Hübner, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

Data path driven waveform-like reconfiguration

Lars Braun, Jürgen Becker, Michael Hübner, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies

Klaus D. Müller-Glaser, Lars Braun, Jürgen Becker, 2010, Dynamically Reconfigurable Systems.

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

Lars Braun, Jürgen Becker, Michael Hübner, 2010, TRETS.

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2011, 2011 Design, Automation & Test in Europe.

SPP1148 booth: Fine grain reconfigurable architectures

Marco Platzner, Jürgen Teich, Lars Braun, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Two Dimensional Dynamic Multigrained Reconfigurable Hardware

Lars Braun, Jürgen Becker, 2010, ISVLSI.

A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker

Lars Braun, Jürgen Becker, Michael Hübner, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Run-time resource instantiation for fault tolerance in FPGAs

Luigi Carro, Lars Braun, Jürgen Becker, 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Two-Dimensional Dynamic Multigrained Reconfigurable Hardware

Lars Braun, Jürgen Becker, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2010, ISVLSI.

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

Bin Zhang, Lars Braun, Jürgen Becker, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Data reallocation by exploiting FPGA configuration mechanisms

Lars Braun, Jürgen Becker, Michael Hübner, 2008, ARC.

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Gert F. Trommer, Lars Braun, Jürgen Becker, 2011, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP).

An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores

Lars Braun, Jürgen Becker, Alexander Klimm, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

Wayne Luk, Lars Braun, Georgi Kuzmanov, 2011 .

Fine grain reconfigurable architectures.

Marco Platzner, Jürgen Teich, Lars Braun, 2008, FPL 2008.

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Lars Braun, Jürgen Becker, Michael Hübner, 2009, Journal of Real-Time Image Processing.

Dynamic Processor Reconfiguration

Jörg Henkel, Lars Braun, Jürgen Becker, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

Lars Braun, Jürgen Becker, Michael Hübner, 2007, 2007 International Conference on Field Programmable Logic and Applications.

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing

Lars Braun, Jürgen Becker, Michael Hübner, 2009, ARC.

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems

Lars Braun, Jürgen Becker, Michael Hübner, 2004, FPL.