Tad Kwasniewski

发表

An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel

Bo Wang, Dianyong Chen, Bangli Liang, 2009, 2009 International Conference on Communications, Circuits and Systems.

0.18 [micro sign]m CMOS backplane receiver with decision-feedback equalisation embedded

Miao Li, Tad Kwasniewski, W. Huang, 2006 .

An architecture independent test methodology for SRAM FPGAs

V. Szwarc, Tad Kwasniewski, G. S. Bhullar, 1997, CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings.

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Tad Kwasniewski, M. Thamsirianunt, 1997 .

DFE architectures for high-speed backplane applications

Tad Kwasniewski, M. Li, S. Wang, 2005 .

A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link

Tad Kwasniewski, Nathan Kiddinapillai, 2009, 2009 NORCHIP.

Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

Tad Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2003 .

On AZ Fractional-N Frequency Synthesizers

Tad Kwasniewski, Farhad Zarkeshvari, Peter Noel, 2009 .

Analysis and Simulation of Phase Noise in Distributed Oscillators

Jing Zhang, Tad Kwasniewski, Haitao Mei, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Pipelined digital design in SRAM FPGAs

V. Szwarc, Tad Kwasniewski, H. Ho, 1997, CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings.

Prediction of Phase Noise in CMOS Distributed

Jing Zhang, Tad Kwasniewski, Haitao Mei, 2003 .

On-die power grid broadband model determination using a priori narrowband measurements

Tad Kwasniewski, Xin Jie Wang, Leonard MacEachem, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Design and implementation of a reconfigurable polyphase-fft system

V. Szwarc, Tad Kwasniewski, H. Ho, 2004 .

Design and FPGA implementation of a multicarrier baseband processor

V. Szwarc, Tad Kwasniewski, H. Ho, 2003 .

Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain

Tad Kwasniewski, Xin Jie Wang, 2016, IEEE Transactions on Electromagnetic Compatibility.

A 1.25 GHz 0.35 /spl mu/m monolithic CMOS PLL clock generator for data communications

Tad Kwasniewski, Lizhong Sun, T. Kwasniewski, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

A mixed-mode sampled-data simulation program

M. A. Copeland, Tad Kwasniewski, G. P. Bell, 1987 .

FIR filter optimisation as pre-emphasis of high-speed backplane data transmission

Miao Li, Tad Kwasniewski, Yuming Tao, 2004 .

Design and optimization of edge equalizer for high-speed electrical backplane

Bo Wang, Dianyong Chen, Bangli Liang, 2009, 2009 7th International Conference on Information, Communications and Signal Processing (ICICS).

Unifying approach for jitter transfer analysis of bang-bang CDR circuits

Tad Kwasniewski, Ahmed Gabr, 2010, 2010 International Conference on Electronics and Information Engineering.

Reduced-complexity trellis coding/decoding for high bit rate digital subscriber loop transmission

David Falconer, Tad Kwasniewski, Vilas Joshi, 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.