Weixun Cao

High-speed parallel VLSI-architecture for the (24,12) Golay decoder with optimized permutation decoding

Weixun Cao, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

An Example of Passion/Product/Project-Based Learning for K-12 Steam Education

Weixun Cao, Xiaoya Yu, Duanyan Zhou, 2017 .

Hierarchies of Understanding for Human Learning

Weixun Cao, Scott A. Carpenter, Catherine Liu, 2018, 2018 IEEE Frontiers in Education Conference (FIE).

Hierarchies of Understanding: Preparing for A.I

Weixun Cao, Scott A. Carpenter, Catherine Liu, 2018, HCI.

Learning and Collaboration Technologies. Design, Development and Technological Innovation

Weixun Cao, Scott A. Carpenter, Catherine Liu, 2018, Lecture Notes in Computer Science.

High-speed parallel hard and soft-decision Golay decoder: algorithm and VLSI-architecture

Weixun Cao, 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

A CODEC CHIP ARCHITECTURE FOR (24,12,8) GOLAY CODE WITH THE PERMUTATION DECODING

Ernst Eberlein, Dieter Seitzer, Weixun Cao, 1992 .

An innovative classroom that produces innovative students

Hong Gao, Zhiqiang Xu, Weixun Cao, 2013, 2013 IEEE Frontiers in Education Conference (FIE).