Praveen K. Murthy

Praveen K. Murthy, Etan G. Cohen, Steve Rowland, 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).

Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003

Praveen K. Murthy, Paolo Faraboschi, Thomas M. Conte, 2003, CASES.

Renesting Single Appearance Schedules to Minimize Buffer Memory

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1995 .

Scheduling for Embedded Real-Time Systems

Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Praveen K. Murthy, 1998, IEEE Des. Test Comput..

Synthesis of Embedded Software from Synchronous Dataflow Specifications

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1999, J. VLSI Signal Process..

Shared buffer implementations of signal processing systems usinglifetime analysis techniques

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Two Complementary Heuristics for Translating Graphical DSP Programs into Minimum Memory Implementati

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1995 .

A Generalization of Multidimensional Synchronous Dataflow to Arbitrary Sampling Lattices

Edward A. Lee, Praveen K. Murthy, 1995 .

Loose Interdependence Algorithms

Edward A. Lee, Praveen K. Murthy, Shuvra S. Battacharyya, 1996 .

Joint Code and Data Minimization

Edward A. Lee, Praveen K. Murthy, Shuvra S. Battacharyya, 1996 .

Approximation Algorithms and Heuristics for the Dynamic StorageAllocation Problem

Praveen K. Murthy, Shuvra S. Bhattacharyya, 1999 .

Converting graphical DSP programs into memory constrained software prototypes

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1995, Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.

The CBP parameter --- a useful annotation to aid SDF compilers

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2000 .

Minimizing memory requirements for chain-structured synchronous dataflow programs

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

The CBP parameter-a useful annotation to aid block-diagram compilers for DSP

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Compact Procedural Synthesis of DSP Software Through Recursive Graph Decomposition

Praveen K. Murthy, Shuvra S. Bhattacharyya, Ming-Yung Ko, 2006 .

Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls

Praveen K. Murthy, Shuvra S. Bhattacharyya, Ming-Yung Ko, 2007, TECS.

Shared memory implementations of synchronous dataflow specifications

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2000, DATE '00.

Notation and Background

Praveen K. Murthy, Shuvra S. Bhattacharyya, S. Bhattacharyya, 2006 .

A Generalization of Multidimensional Synchronous Dataflow to

Edward A. Lee, Praveen K. Murthy, 1999 .

High level hardware validation using hierarchical message sequence charts

Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

Software Synthesis from Dataflow Graphs

Edward A. Lee, Praveen K. Murthy, Shuvra S. Battacharyya, 1996 .

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1997, Des. Autom. Embed. Syst..

Optimal parenthesization of lexical orderings for DSP block diagrams

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1995, VLSI Signal Processing, VIII.

Systematic consolidation of input and output buffers in synchronous dataflow specifications

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

Compact Procedural Im plementation in D SP Software Syn th esis through Recu r sive Grap h Decomposition

Praveen K. Murthy, Shuvra S. Bhattacharyya, Ming-Yung Ko, 2004 .

Cases 2003 : International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 30 - November 1, 2003, San Jose, California, USA

Praveen K. Murthy, Jaime H. Moreno, 2003 .

Buffer merging—a powerful technique for reducing memory requirements of synchronous dataflow specifications

Praveen K. Murthy, Shuvra S. Bhattacharyya, S. Bhattacharyya, 2004, TODE.

Minimizing Memory Requirements for Chain-Structured SDF Graphs

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1994 .

Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition

Praveen K. Murthy, Shuvra S. Bhattacharyya, Ming-Yung Ko, 2004, SCOPES.

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2004, J. VLSI Signal Process..

Optimized software synthesis for synchronous dataflow

Edward A. Lee, Praveen K. Murthy, Shuvra S. Bhattacharyya, 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

Effective Strategies for Aggressive Memory Optimization

Praveen K. Murthy, Shuvra S. Bhattacharyya, 2006 .

Multidimensional synchronous dataflow

Edward A. Lee, Praveen K. Murthy, P. Murthy, 2002, IEEE Trans. Signal Process..