H. Adhikari

Adjusting to 3D devices in a 2D device world

C.E. Smith, P. Majhi, G. Smith, 2008, 2008 IEEE International SOI Conference.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

R. Jammy, Jiyoung Kim, P. Majhi, 2006, 2009 Symposium on VLSI Technology.

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node

R. Jammy, P. D. Kirsch, P. Majhi, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).