S. Watanabe

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

T. Ohsawa, T. Higashi, T. Furuyama, 2006, IEEE Journal of Solid-State Circuits.

A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic]

K. Sunouchi, A. Toriumi, Y. Oowaki, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change

S. Watanabe, Masaru Kikuchi, Tetsuo Nomoto, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

M. Terauchi, Y. Oowaki, A. Ohta, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Computation with a parallel FDTD system of human-body effect on electromagnetic absorption for portable telephones

S. Watanabe, Y. Yamanaka, O. Fujiwara, 2004, IEEE Transactions on Microwave Theory and Techniques.

A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change

S. Watanabe, Masaru Kikuchi, Tetsuo Nomoto, 2006, IEEE Journal of Solid-State Circuits.

A 12/24 GHz frequency doubler MMIC using resistive series feedback circuit

Y. Shizuki, Y. Fuchida, F. Sasaki, 1999, 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282).